Non-volatile memory device conducting comparison operation

Abstract

The non-volatile memory device includes a current detection circuit for comparing, in data retrieve operation, storage information written in a non-volatile manner in a memory cell row with retrieval information in order to determine whether or not the storage information matches the retrieval information. The current detection circuit compares a data read current flowing through each bit line corresponding to each memory cell of a memory cell row storing the storage information with a data read current flowing through each bit line corresponding to each retrieval memory cell storing the retrieval information.

What is claimed is:  
     
         1 . A non-volatile memory device, comprising: 
 a plurality of memory cells arranged in a matrix, and each having an electric resistance varying according to storage data written in a non-volatile manner by a data write current; and    a plurality of word lines provided corresponding to memory cell rows respectively, wherein 
 memory cells of a predetermined memory cell row of said memory cell rows have retrieval information, and memory cells of other memory cell rows of said memory cell rows have storage information,  
 the non-volatile memory device further comprising: 
 a comparison circuit for comparing in data retrieve operation said retrieval information read from said predetermined memory cell row with said storage information read from one of said other memory cell rows which is designated for said data retrieve operation.  
 
   
     
     
         2 . The non-volatile memory device according to  claim 1 , wherein each of said memory cells stores one-bit data of one of said storage information and said retrieval information.  
     
     
         3 . The non-volatile memory device according to  claim 1 , wherein, in said data retrieve operation, said comparison circuit compares a passing current generated in each of said memory cells of said predetermined memory cell row in response to activation of a word line corresponding to said predetermined memory cell row with a passing current generated in each of said memory cells of said one of said other memory cell rows in response to activation of a word line corresponding to said one of said other memory cell rows.  
     
     
         4 . The non-volatile memory device according to  claim 1 , wherein 
 said plurality of memory cells are divided into a plurality of memory blocks, and    said storage information to be compared with said retrieval information stored in one memory block of said plurality of memory blocks in said data retrieve operation is stored in another memory block of said plurality of memory blocks.    
     
     
         5 . The non-volatile memory device according to  claim 4 , wherein 
 each of said memory blocks includes said predetermined memory cell row, said other memory cell rows, and a plurality of bit lines provided corresponding to memory cell columns respectively, and    said comparison circuit compares a passing current generated on each of said bit lines in said one memory block in response to activation of a word line corresponding to said predetermined memory cell row included in said one memory block with a passing current generated on each of said plurality of bit lines in said another memory block in response to activation of a selected word line corresponding to a selected one of said other memory cell rows included in said another memory block.    
     
     
         6 . The non-volatile memory device according to  claim 5 , wherein 
 said comparison circuit includes a plurality of current comparison circuits provided respectively corresponding to said plurality of bit lines, and a determination circuit for outputting a determination result of whether said storage information matches said retrieval information,    each of said current comparison circuits compares a passing current on the corresponding bit line generated based on said retrieval information in said predetermined memory cell row included in said one memory block with a passing current on the corresponding bit line of the same column generated based on said storage information in said one of said other memory cell rows included in said another memory block, and    said determination circuit outputs said determination result based on a comparison result of each of said plurality of current comparison circuits.    
     
     
         7 . The non-volatile memory device according to  claim 5 , further comprising: 
 a mask circuit for ceasing comparison between a passing current on a part of said plurality of bit lines in said one memory block and a passing current on a part said plurality of bit lines in said another memory block conducted by said comparison circuit in said data retrieve operation, wherein 
 said mask circuit ceases comparison between a passing current on each of bit lines corresponding to memory cells other than a memory cell storing one-bit data of said retrieval information of said predetermined memory cell row and a passing current on each of bit lines of the same column corresponding to memory cells of one of said other memory cell rows.  
   
     
     
         8 . The non-volatile memory device according to  claim 5 , further comprising: 
 a plurality of first sense amplifiers provided respectively corresponding to said plurality of bit lines included in said one memory block storing said retrieval information, each first sense amplifier generating a first voltage signal based on a difference between a current passing through a corresponding bit line and a predetermined current, and outputting said first voltage signal to said comparison circuit; and    a plurality of second sense amplifiers provided respectively corresponding to said plurality of bit lines included in said another memory block storing said storage information, each second sense amplifier generating a second voltage signal based on a difference between a current passing through a corresponding bit line and said predetermined current, and outputting said second voltage signal to said comparison circuit, wherein 
 said comparison circuit determines whether said retrieval information matches said storage information based on said first and second voltage signals received from the corresponding first and second amplifiers in each of said bit lines.  
   
     
     
         9 . The non-volatile memory device according to  claim 5 , wherein 
 said comparison circuit includes 
 a current line,  
 a current supply source for supplying a first current amount to said current line,  
 a plurality of current extraction circuits provided respectively corresponding to said plurality of bit lines, each current extraction circuit extracting a second current amount from a current amount flowing through said current line according to comparison between a passing current generated on each of said bit lines in said one memory block based on said retrieval information and a passing current generated on each of said bit lines in said another memory block based on said storage information, and  
 a determination circuit provided at a terminal end of said current line, for outputting a determination result according to comparison between said current amount flowing through said current line and a predetermined current amount.  
   
     
     
         10 . A non-volatile memory device, comprising: 
 a memory block having a plurality of memory cells arranged in a matrix and each having an electric resistance varying according to storage data written in a non-volatile manner by a data write current; and    a comparison circuit for conducting comparison of retrieval information received from outside in data retrieve operation, wherein 
 said comparison circuit includes a storage section for temporal data storage,  
 said non-volatile memory device further comprising: 
 a control circuit for transferring storage information pre-stored in said memory block to said storage section in said data retrieve operation, and  
 said comparison circuit compares said storage information transferred to said storage section with said retrieval information in order to determine whether said storage information matches said retrieval information.  
 
   
     
     
         11 . A non-volatile memory device, comprising: 
 a plurality of memory cells arranged in a matrix, and each having an electric resistance varying according to storage data written in a non-volatile manner by a data write current;    a plurality of word lines provided corresponding to memory cell rows respectively;    a plurality of bit lines provided corresponding to memory cell columns respectively;    a selection circuit for selecting one of a memory cell row and a memory cell column; and    a control circuit for continuously conducting one of data write operation and data read operation to a memory cell group said one of said memory cell row and said memory cell column selected by said selection circuit.    
     
     
         12 . The non-volatile memory device according to  claim 11 , wherein said control circuit conducts said one of said data write operation and said data read operation to each memory cell of said memory cell group on a bit-by-bit basis.  
     
     
         13 . A non-volatile memory device, comprising: 
 a plurality of memory cells arranged in a matrix, and each having an electric resistance varying according to storage data written in a non-volatile manner by a data write current;    a plurality of word lines provided corresponding to memory cell rows respectively;    a plurality of bit lines provided corresponding to memory cell columns respectively; and    a control circuit for conducting one of data write operation and data read operation wherein 
 each of data write operation and data read operation is divided into a plurality of cycles, said control circuit conducts a part of said one of data write operation and data read operation in each of said cycles by pipeline processing.  
   
     
     
         14 . The non-volatile memory device according to  claim 13 , further comprising: 
 an address latch circuit for temporarily holding information for selecting a memory cell row and a memory cell column, wherein 
 said address latch circuit operates in synchronization with each of said plurality of cycles.  
   
     
     
         15 . The non-volatile memory device according to  claim 13 , further comprising: 
 a data latch circuit for temporarily holding data transmitted between a selected memory cell and a data output node, wherein 
 said data latch circuit operates in synchronization with each of said plurality of cycles.