Nonvolatile semiconductor memory device having improved redundancy relieving rate

Abstract

In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.

What is claimed is:  
     
         1 . A nonvolatile semiconductor memory device comprising: 
 a plurality of normal memory cells each storing data of one bit in a nonvolatile manner;    a plurality of spare memory cells each used in place of a defective memory cell when the defective memory cell is present in said plurality of normal memory cells, and constituted so that two spare memory cells store data of one bit as a whole;    a control circuit, in accordance with an external access, selecting a first memory cell group corresponding to an address signal from among said plurality of normal memory cells and selecting a second memory cell group from among said plurality of spare memory cells in parallel to selection of said first memory cell group; and    a select and amplification section selecting a read memory cell group in accordance with said address signal from among said first and second memory cell groups, and amplifying and outputting the data held in said read memory cell group.    
     
     
         2 . The nonvolatile semiconductor memory device according to  claim 1 , further comprising: 
 a data line group for reading the data from said first and second memory cell groups, wherein 
 said select and amplification section includes: 
 a plurality of sense amplifier circuits as many as memory cells included in said read memory cell group; and  
 a select section selectively connecting a part of said data line group transmitting the data to be read in accordance with said address signal, to said plurality of sense amplifier circuits.  
 
   
     
     
         3 . The nonvolatile semiconductor memory device according to  claim 1 , wherein 
 said plurality of normal memory cells are arranged in rows and columns, and    said nonvolatile semiconductor memory device further comprising: 
 a plurality of word lines provided along said rows of said plurality of normal memory cells;  
 a plurality of bit lines provided along said columns of said plurality of normal memory cells;  
 a plurality of reference memory cells provided adjacent to a region in which said plurality of normal memory cells are arranged, arranged to form columns along a column direction of said plurality of normal memory cells, and each holding a reference value for determining a read value when the data is read from each of said normal memory cells;  
 first and second data lines, one of the first and second data lines being connected to one of said plurality of normal memory cells and the other being connected to one of said plurality of reference memory cells; and  
 third and fourth data lines connected to first and second spare memory cells, among said plurality of spare memory cells, forming a pair and storing predetermined data of one bit as the pair.  
   
     
     
         4 . The nonvolatile semiconductor memory device according to  claim 1 , wherein 
 said plurality of normal memory cells are arranged in rows and columns, and    said nonvolatile semiconductor memory device further comprising: 
 a plurality of digit lines each provided corresponding to each of said rows of said plurality of normal memory cells; and  
 a plurality of word lines, two word lines provided corresponding to each of said rows of said plurality of normal memory cells, for selecting the rows during data read,  
   said plurality of normal memory cells in each row are alternately connected to corresponding two of said word lines, and    said nonvolatile semiconductor memory device further comprising: 
 a plurality of reference memory cells provided adjacent to a region in which said plurality of normal memory cells are arranged, arranged to form rows along a row direction of said plurality of normal memory cells, and each holding a reference value for determining a read value when reading the data from each of said normal memory cells.  
   
     
     
         5 . A nonvolatile semiconductor memory device comprising: 
 a plurality of normal memory cells;    a plurality of spare memory cells each used in place of a defective memory cell when the defective memory cell is present in said plurality of normal memory cells;    a first data line group for reading a first data group from said plurality of normal memory cells in accordance with an external access;    a second data line group for reading a second data group from said plurality of spare memory cells in parallel to reading of said first data group; and    a select and amplification section selectively amplifying and outputting a read data group in accordance with an address signal, from said first and second data groups.    
     
     
         6 . The nonvolatile semiconductor memory device according to  claim 5 , wherein 
 said select and amplification section includes: 
 a plurality of sense amplifier circuits as many as the data included in said read data group; and  
 a select section selectively connecting a part of said first and second data line groups transmitting the data to be read in accordance with said address signal, to said plurality of sense amplifier circuits.  
   
     
     
         7 . The nonvolatile semiconductor memory device according to  claim 6 , further comprising: 
 a redundancy control section receiving said address signal, and detecting whether an address corresponds to an address indicating said defective memory cell, wherein 
 a plurality of data lines included in said first and second data line groups are aligned in a predetermined order, and  
 said select section shifts the data lines selected from among said first and second data line groups in accordance with an output of said redundancy control section without changing said predetermined order, and connects the selected data lines to said plurality of sense amplifiers.  
   
     
     
         8 . A nonvolatile semiconductor memory device comprising: 
 a plurality of normal memory cells;    a plurality of spare memory cells each used in place of a defective memory cell when the defective memory cell is present in said plurality of normal memory cells; and    a program array storing an address of said defective memory cell in a nonvolatile manner, wherein 
 said program array includes 
 a plurality of program sets,  
 each of said plurality of program sets has  
 a first program unit consisting of nonvolatile memory cells equal in structure to said normal memory cells, and storing a flag bit indicating whether the corresponding program set is already programmed to store the address of the defective memory cell, and  
 a second program unit storing the address of the defective memory cell, and  
 
 said nonvolatile semiconductor memory device further comprising: 
 a select circuit selecting a part of the plurality of flag bits corresponding to said plurality of program sets, respectively, in accordance with addresses of the program sets; and  
 a terminal for reading an output of said select circuit to an outside of the nonvolatile semiconductor memory device.  
 
   
     
     
         9 . The nonvolatile semiconductor memory device according to  claim 8 , wherein 
 said program array further includes: 
 a voltage switching circuit selectively applying an external high voltage to said first program unit so as to irreversibly destroy a nonvolatile memory cell included in said first program unit so that the frag bit indicates that the corresponding program set is already programmed.  
   
     
     
         10 . The nonvolatile semiconductor memory device according to  claim 8 , wherein 
 said plurality of spare memory cells are arranged to be divided into a plurality of replacement units, and    said plurality of program sets are fewer than said plurality of replacement units.    
     
     
         11 . The nonvolatile semiconductor memory device according to  claim 8 , wherein 
 said plurality of spare memory cells are arranged to be divided into a plurality of replacement units, and    each of said program sets further has    a third program unit storing information for designating one of said plurality of replacement units.    
     
     
         12 . The nonvolatile semiconductor memory device according to  claim 8 , wherein 
 each of said program sets further has    a consistency detection section detecting whether an address corresponding to the stored defective memory cell coincides with an input address, and    said nonvolatile semiconductor memory device further comprising 
 a write driver deactivating a write signal written to said normal memory cell in accordance with an output of said consistency detection section.