Method and apparatus for enabling a stitch wire bond in the absence of discrete bump formation, semiconductor device assemblies and electronic systems including same

Abstract

An apparatus and method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the wafer in at least one electroless bath having a nickel-containing solution therein, wherein bumps having a nickel-containing material are formed simultaneously on the exposed bond pads to an elevation sufficient to prevent damage to a passivation layer surrounding the bond pads by contact of a wire bonding capillary. A gold or palladium cap may optionally be formed over the nickel-containing material of the bumps.

What is claimed is:  
     
         1 . A bumped semiconductor device, comprising: 
 at least one semiconductor die having an active surface and a back surface, the active surface having a plurality of bond pads thereon exposed through a passivation layer; and    at least one bump formed over at least one of the bond pads, the at least one plated bump comprising a nickel-containing material and extending at least to an elevation of an outer surface of the passivation layer.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the at least one bump comprises a plated nickel material.  
     
     
         3 . The semiconductor device of  claim 2 , wherein the at least one bump comprises a plated gold material over the plated nickel material.  
     
     
         4 . The semiconductor device of  claim 2 , wherein the at least one bump comprises a plated palladium material over the plated nickel material.  
     
     
         5 . The semiconductor device of  claim 3 , wherein the plated gold material comprises a cap extending completely over the plated nickel material.  
     
     
         6 . The semiconductor device of  claim 1 , wherein the bond pads comprise an aluminum material.  
     
     
         7 . The semiconductor device of  claim 1 , wherein the at least one bump comprises an outer surface displaced above the outer surface of the passivation layer.  
     
     
         8 . The semiconductor device of  claim 1 , wherein the at least one bump comprises an outer surface substantially coplanar with the outer surface of the passivation layer.  
     
     
         9 . The semiconductor device of  claim 7 , wherein the outer surface of the at least one bump is displaced above the outer surface of the passivation layer about 0.2 microns to 2.5 microns.  
     
     
         10 . The semiconductor device of  claim 1 , wherein the at least one bump substantially overlies an entire exposed surface of the at least one bond pad.  
     
     
         11 . The semiconductor device of  claim 1 , wherein the at least one semiconductor die comprises a wafer bearing a plurality of semiconductor dice.  
     
     
         12 . The semiconductor device of  claim 1 , wherein the at least one bump comprises a nickel layer of up to about 5 microns thickness.  
     
     
         13 . The semiconductor device of  claim 12 , wherein the at least one bump further comprises a gold layer of about 0.05 micron thickness.  
     
     
         14 . The semiconductor device of  claim 12 , wherein the at least one bump further comprises a gold layer of between about 0.6 and 0.8 micron thickness.  
     
     
         15 . The semiconductor device of  claim 1 , wherein the at least one bond pad comprises an end of a trace of a redistribution layer.  
     
     
         16 . A wafer, comprising: 
 a semiconductor wafer having an active surface and a back surface, the active surface having a passivation layer formed thereon and bond pads exposed through the passivation layer; and    bumps formed over at least some of the bond pads on the active surface, the bumps comprising a nickel-containing material and extending at least to an elevation of an outer surface of the passivation layer.    
     
     
         17 . The wafer of  claim 16 , wherein the semiconductor wafer comprises rows and columns of unsingulated semiconductor dice each bearing a plurality of bond pads.  
     
     
         18 . The wafer of  claim 17 , wherein each of the semiconductor dice includes at least some bumps formed on bond pads thereof.  
     
     
         19 . The wafer of  claim 16 , wherein the bumps each comprise an outer surface displaced above the outer surface of the passivation layer.  
     
     
         20 . The wafer of  claim 16 , wherein the bumps each comprise an outer surface substantially coplanar with the outer surface of the passivation layer.  
     
     
         21 . The wafer of  claim 19 , wherein the outer surface of each of the bumps is displaced above the outer surface of the passivation layer about 0.2 microns to 2.5 microns.  
     
     
         22 . The wafer of  claim 16 , wherein the bumps substantially overlie the bond pads.  
     
     
         23 . The wafer of  claim 16 , wherein the bumps comprise a plated nickel material.  
     
     
         24 . The wafer of  claim 23 , wherein the bumps further comprise a plated gold material over the plated nickel material.  
     
     
         25 . The wafer of  claim 23 , wherein the bumps further comprise a plated palladium material over the plated nickel material.  
     
     
         26 . The wafer of  claim 16 , wherein the bumps each comprise a nickel layer of up to about 5 microns thickness.  
     
     
         27 . The wafer of  claim 26 , wherein the bumps each further comprise a gold layer of about 0.05 micron thickness.  
     
     
         28 . The wafer of  claim 26 , wherein the bumps each comprise a gold layer of between about 0.6 and 0.8 micron thickness.  
     
     
         29 . The wafer of  claim 16 , wherein at least some of the bond pads comprise an end of a trace of a redistribution layer.  
     
     
         30 . A semiconductor device assembly comprising: 
 a semiconductor substrate having an active surface and a back surface, the active surface having bond pads thereon exposed through a passivation layer and bumps formed over at least some of the bond pads, the bumps comprising a nickel material;    a carrier substrate having conductive portions exposed on a surface thereof, the carrier substrate attached to the semiconductor substrate; and    bond wires extending between the conductive portions on the surface of the carrier substrate and the bumps on the active surface of the semiconductor substrate.    
     
     
         31 . The semiconductor device assembly of  claim 30 , wherein at least some of the bumps are arranged proximate a periphery of the active surface of the semiconductor substrate.  
     
     
         32 . The semiconductor device assembly of  claim 31 , wherein the back surface of the semiconductor substrate is attached to the surface of the carrier substrate.  
     
     
         33 . The semiconductor device assembly of  claim 30 , wherein at least some of the bumps are centrally aligned on the active surface of the semiconductor substrate.  
     
     
         34 . The semiconductor device assembly of  claim 33 , wherein the carrier substrate comprises a slot defined therein and extending between the surface of the carrier substrate and an opposing, second surface of the carrier substrate and the active surface of the semiconductor substrate is attached to the second surface of the carrier substrate so that the bumps are exposed through the slot.  
     
     
         35 . The semiconductor device assembly of  claim 30 , further comprising a dielectric encapsulation material encapsulating at least bumps and the bond wires.  
     
     
         36 . The semiconductor device assembly of  claim 30 , wherein the semiconductor substrate comprises at least one semiconductor die.  
     
     
         37 . The semiconductor device assembly of  claim 30 , wherein the bumps each comprise an outer surface displaced above an outer surface of the passivation layer.  
     
     
         38 . The semiconductor device assembly of  claim 30 , wherein the bumps each comprise an outer surface substantially coplanar with an outer surface of the passivation layer.  
     
     
         39 . The semiconductor device assembly of  claim 37 , wherein the outer surface of each of the bumps is displaced above the outer surface of the passivation layer about 0.2 microns to 0.5 microns.  
     
     
         40 . The semiconductor device assembly of  claim 30 , wherein the bumps substantially overlie the bond pads.  
     
     
         41 . The semiconductor device assembly of  claim 30 , wherein the bumps comprise a plated nickel material.  
     
     
         42 . The semiconductor device assembly of  claim 41 , wherein the bumps further comprise a plated gold material over the plated nickel material.  
     
     
         43 . The semiconductor device assembly of  claim 41 , wherein the bumps further comprise a plated palladium material over the plated nickel material.  
     
     
         44 . The semiconductor device assembly of  claim 30 , wherein the bumps each comprise a nickel layer of up to about 5 microns thickness.  
     
     
         45 . The semiconductor device assembly of  claim 44 , wherein the bumps each further comprise a gold layer of about 0.05 micron thickness.  
     
     
         46 . The semiconductor device assembly of  claim 44 , wherein the bumps each comprise a gold layer of between about 0.6 and 0.8 micron thickness.  
     
     
         47 . The semiconductor device assembly of  claim 30 , wherein at least some of the bond pads comprise an end of a trace of a redistribution layer.  
     
     
         48 . A method of bumping wafers, comprising: 
 providing at least one wafer having an active surface and a back surface, the active surface having bond pads exposed thereon through a passivation layer; and    disposing the at least one wafer in at least one bath including a nickel material to form a nickel-containing bump on each of the exposed bond pads.    
     
     
         49 . The method of  claim 48 , wherein disposing comprises disposing the at least one wafer in at least one of an electroless bath and an electrolytic bath.  
     
     
         50 . The method of  claim 48 , wherein disposing comprises disposing multiple wafers simultaneously in the at least one bath.  
     
     
         51 . The method of  claim 48 , further comprising disposing the at least one wafer in at least another bath including a gold material to form a gold-containing cap over each of the nickel-containing bumps.  
     
     
         52 . The method of  claim 48 , further comprising disposing the at least one wafer in at least another bath including a palladium material to form a palladium-containing cap over each of the nickel-containing bumps.  
     
     
         53 . The method of  claim 48 , wherein disposing comprises forming the nickel-containing bumps with an outer surface thereof displaced above an outer surface of the passivation layer.  
     
     
         54 . The method of  claim 48 , wherein disposing comprises forming the nickel-containing bumps with an outer surface thereof substantially coplanar with an outer surface of the passivation layer.  
     
     
         55 . The method of  claim 48 , wherein forming comprises forming the nickel-containing bumps with an outer surface thereof displaced above an outer surface of the passivation layer approximately 0.2 microns to 2.5 microns.  
     
     
         56 . A method of forming a semiconductor device assembly, the method comprising: 
 providing at least one semiconductor die having an active surface with bond pads formed thereon and a back surface, the bond pads being exposed through a passivation layer and each of the bond pads including a nickel-containing bump formed thereon;    providing a carrier substrate having conductive portions exposed on a surface thereof; and    attaching the at least one semiconductor die to the surface of the carrier substrate in a location and orientation exposing the nickel-containing bumps on the bond pads; and    bonding bond wires to the nickel-containing bumps on the active surface and to the conductive portions of the carrier substrate without contacting the passivation layer with a wire bond capillary.    
     
     
         57 . The method of  claim 56 , wherein providing the at least one semiconductor die comprises forming each of the nickel-containing bumps with an outer surface thereof displaced above an outer surface of the passivation layer.  
     
     
         58 . The method of  claim 56 , wherein providing the at least one semiconductor die comprises forming each of the nickel-containing bumps with an outer surface thereof substantially coplanar with an outer surface of the passivation layer.  
     
     
         59 . The method of  claim 56 , wherein providing the at least one semiconductor die comprises forming each of the nickel-containing bumps with an outer surface thereof displaced above an outer surface of the passivation layer approximately 0.2 microns to 2.5 microns.  
     
     
         60 . The method of  claim 56 , wherein providing the at least one semiconductor die comprises providing the at least one semiconductor die with at least some of the nickel-containing bumps proximate a periphery of the active surface thereof.  
     
     
         61 . The method of  claim 60 , wherein attaching comprises attaching the back surface of the at least one semiconductor die to the surface of the carrier substrate.  
     
     
         62 . The method of  claim 56 , wherein providing the at least one semiconductor die comprises providing the at least one semiconductor die with at least some of the nickel-containing bumps centrally aligned on the active surface thereof.  
     
     
         63 . The method of  claim 62 , wherein providing the carrier substrate comprises providing the carrier substrate with a slot defined therein, wherein the slot extends between the surface of the carrier substrate and an opposing, second surface of the carrier substrate, and wherein attaching comprises attaching the active surface of the at least one semiconductor die to the second surface of the carrier substrate so that the nickel-containing bumps are exposed through the slot.  
     
     
         64 . The method of  claim 56 , further comprising encapsulating at least the nickel-containing bumps and the bond wires with a dielectric encapsulant.  
     
     
         65 . A method of preparing wafers for bonding bond wires thereto, the method comprising: 
 providing at least one wafer having an active surface and a back surface, the active surface having bond pads exposed thereon through a passivation layer;    disposing the at least one wafer in at least one bath including a nickel material to form nickel-containing bumps on each of the exposed bond pads.    
     
     
         66 . The method of  claim 65 , further comprising cleaning the nickel-containing bumps.  
     
     
         67 . The method of  claim 66 , wherein cleaning comprises performing an argon plasma cleaning.  
     
     
         68 . The method of  claim 65 , wherein disposing comprises disposing the at least one wafer in at least one of an electroless bath and an electrolytic bath.  
     
     
         69 . The method of  claim 68 , wherein disposing comprises disposing a plurality of wafers simultaneously.  
     
     
         70 . The method of  claim 65 , further comprising disposing the at least one wafer in at least another bath including a gold material to form a gold-containing cap over each of the nickel-containing bumps.  
     
     
         71 . The method of  claim 65 , further comprising disposing the at least one wafer in at least another bath including a palladium material to form a palladium-containing cap over each of the nickel-containing bumps.  
     
     
         72 . The method of  claim 65 , wherein disposing comprises forming the nickel-containing bumps with an outer surface thereof displaced above an outer surface of the passivation layer.  
     
     
         73 . The method of  claim 65 , wherein disposing comprises forming the nickel-containing bumps with an outer surface thereof substantially coplanar with an outer surface of the passivation layer.  
     
     
         74 . The method of  claim 65 , wherein disposing comprises forming the nickel-containing bumps with an outer surface thereof displaced above the outer surface of the passivation layer approximately 0.2 microns to 2.5 microns.  
     
     
         75 . An electronic system comprising: 
 a processor device coupled to an input device and an output device; and    a semiconductor device assembly coupled to at least one of the processor device, the input device and the output device, the semiconductor device assembly comprising: 
 a semiconductor substrate having an active surface and a back surface, the active surface having bond pads thereon exposed through a passivation layer and bumps formed over at least some of the bond pads, the bumps comprising a nickel material;  
 a carrier substrate having conductive portions exposed on a surface thereof, the carrier substrate attached to the semiconductor substrate; and  
 bond wires extending between the conductive portions on the surface of the carrier substrate and the bumps on the active surface of the semiconductor substrate.  
   
     
     
         76 . The electronic system of  claim 75 , wherein at least some of the bumps are arranged proximate a periphery of the active surface of the semiconductor substrate.  
     
     
         77 . The electronic system of  claim 76 , wherein the back surface of the semiconductor substrate is attached to the surface of the carrier substrate.  
     
     
         78 . The electronic system of  claim 75 , wherein at least some of the bumps are centrally aligned on the active surface of the semiconductor substrate.  
     
     
         79 . The electronic system of  claim 78 , wherein the carrier substrate comprises a slot defined therein and extending between the surface of the carrier substrate and an opposing, second surface of the carrier substrate, and wherein the active surface of the semiconductor substrate is attached to the second surface of the carrier substrate so that the bumps are exposed through the slot.  
     
     
         80 . The electronic system of  claim 75 , further comprising an encapsulation material encapsulating at least the bumps and the bond wires.  
     
     
         81 . The electronic system of  claim 75 , wherein the semiconductor substrate comprises at least one semiconductor die.  
     
     
         82 . The electronic system of  claim 75 , wherein the bumps each comprise an outer surface displaced above an outer surface of the passivation layer.  
     
     
         83 . The electronic system of  claim 75 , wherein the bumps each comprise an outer surface substantially coplanar with an outer surface of the passivation layer.  
     
     
         84 . The electronic system of  claim 75 , wherein outer surfaces of each of the bumps are displaced above the outer surface of the semiconductor substrate about 0.2 microns to 2.5 microns.  
     
     
         85 . The electronic system of  claim 75 , wherein the bumps each additionally comprise an outer layer of one of a gold-containing material and a palladium-containing material.