Double bumping of flexible substrate for first and second level interconnects

Abstract

An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.

What is claimed is:  
     
         1 . A semiconductor device assembly, comprising: 
 at least one semiconductor die having an active surface and a back surface, the active surface having bond pads thereon; and    an interposer substrate having a first surface having conductive bumps protruding therefrom and a second surface, the conductive bumps protruding from the first surface bonded to the bond pads on the at least one semiconductor die.    
     
     
         2 . The semiconductor device assembly of  claim 1 , further comprising a dielectric filler material disposed between the at least one semiconductor die and the interposer substrate.  
     
     
         3 . The semiconductor device assembly of  claim 2 , wherein the dielectric filler material comprises one of a flowable material and a non-flowable material.  
     
     
         4 . The semiconductor device assembly of  claim 1 , further comprising an encapsulation material formed over the back surface of the at least one semiconductor die.  
     
     
         5 . The semiconductor device assembly of  claim 1 , wherein the interposer substrate comprises a plurality of through holes extending between the first surface and the second surface with conductive bumps positioned in through holes of the plurality and protruding from the second surface of the interposer substrate.  
     
     
         6 . The semiconductor device assembly of  claim 5 , further comprising at least one conductive line on the first surface of the interposer substrate, the at least one conductive line extending between at least one of the plurality of through holes and operably coupled with a conductive bump positioned therein and at least one of the conductive bumps protruding from the first surface.  
     
     
         7 . The semiconductor device assembly of  claim 5 , wherein the conductive bumps positioned in the through holes are preformed prior to positioning.  
     
     
         8 . The semiconductor device assembly of  claim 5 , wherein the conductive bumps protruding from the second surface are arranged to correspond to a pattern of terminal pads on another substrate.  
     
     
         9 . The semiconductor device assembly of  claim 1 , wherein the interposer substrate comprises a flexible material.  
     
     
         10 . The semiconductor device assembly of  claim 1 , wherein the interposer substrate comprises a polymeric material.  
     
     
         11 . The semiconductor device assembly of  claim 5 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise plated masses of metal.  
     
     
         12 . The semiconductor device assembly of  claim 5 , wherein the conductive bumps protruding from the first surface and the conductive, bumps protruding from the second surface comprise at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin, lead and gold.  
     
     
         13 . The semiconductor device assembly of  claim 5 , wherein at least one of the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprises multiple layers of at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin lead and gold.  
     
     
         14 . The semiconductor device assembly of  claim 5 , wherein the conductive bumps protruding from the second surface comprise preformed conductive bumps disposed on a conductive paste within the through holes.  
     
     
         15 . The semiconductor device assembly of  claim 1 , wherein the interposer substrate comprises multiple layers of conductive interconnect lines therein.  
     
     
         16 . The semiconductor device assembly of  claim 1 , wherein the at least one semiconductor die comprises a plurality of semiconductor dice.  
     
     
         17 . The semiconductor device assembly of  claim 1 , wherein the conductive bumps protruding from the first surface are bonded to the bond pads of the at least one semiconductor die through an anisotropically conductive film.  
     
     
         18 . The semiconductor device assembly of  claim 1 , wherein the interposer substrate comprises a plurality of through holes extending between the first surface and the second surface and at least some conductive bumps protruding from the first surface are positioned in through holes of the plurality.  
     
     
         19 . The semiconductor device assembly of  claim 18 , further comprising at least one conductive line on the second surface of the interposer substrate, the at least one conductive line extending between at least one of the plurality of through holes and operably coupled with a conductive bump positioned therein and at least one conductive bump protruding from the second surface.  
     
     
         20 . The semiconductor device assembly of  claim 18 , wherein the conductive bumps positioned in the through holes are preformed prior to positioning.  
     
     
         21 . The semiconductor device assembly of  claim 18 , wherein the conductive bumps protruding from the first surface comprise preformed conductive bumps disposed on a conductive paste within the through holes.  
     
     
         22 . The semiconductor device assembly of  claim 1 , further comprising conductive bumps protruding from the second surface and operably coupled to conductive bumps protruding from the first surface.  
     
     
         23 . The semiconductor device assembly of  claim 22 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface are operably coupled in part with through holes extending at least partially through the interposer substrate.  
     
     
         24 . The semiconductor device assembly of  claim 23 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface are operably coupled in part with conductive lines extending over at least one of the first and second surfaces.  
     
     
         25 . The semiconductor device assembly of  claim 22 , wherein the conductive bumps protruding from the first and second surfaces are formed, at least in part, of a common conductive material.  
     
     
         26 . The semiconductor device assembly of  claim 22 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise plated masses of metal.  
     
     
         27 . The semiconductor device assembly of  claim 22 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin, lead and gold.  
     
     
         28 . The semiconductor device assembly of  claim 22 , wherein at least one of the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprises multiple layers of at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin lead and gold.  
     
     
         29 . An interposer substrate configured to bond with both a first level interconnect and a second level interconnect, the interposer substrate comprising: 
 a substantially planar body having a first surface and a second surface, the first surface having conductive bumps protruding therefrom arranged in a pattern corresponding to a bond pad pattern of at least one semiconductor die and the second surface having conductive bumps protruding therefrom arranged in a pattern corresponding to a terminal pad pattern of a carrier substrate and operably coupled with the conductive bumps protruding from the first surface.    
     
     
         30 . The interposer substrate of  claim 29 , further comprising a non-flowable dielectric filler material disposed over the first surface of the interposer substrate.  
     
     
         31 . The interposer substrate of  claim 29 , further comprising a plurality of through holes extending between the first surface and the second surface and comprising portions of conductive paths extending between conductive bumps respectively protruding from the first and second surfaces.  
     
     
         32 . The interposer substrate of  claim 31 , further comprising at least one conductive line on at least one of the first surface and the second surface and extending between at least one of the through holes and at least one of the conductive bumps.  
     
     
         33 . The interposer substrate of  claim 29 , wherein the substantially planar body comprises a flexible material.  
     
     
         34 . The interposer substrate of  claim 29 , wherein the substantially planar body comprises a polymeric material.  
     
     
         35 . The interposer substrate of  claim 29 , wherein the substantially planar body comprises multiple internal layers of conductive lines connecting at least some of the conductive bumps protruding from the first surface with conductive bumps protruding from the second surface.  
     
     
         36 . The interposer substrate of  claim 29 , wherein at least some of the conductive bumps comprise a plated metal material.  
     
     
         37 . The interposer substrate of  claim 29 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise a common conductive material.  
     
     
         38 . The interposer substrate of  claim 29 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise at least one of a copper, nickel, chromium, zinc, brass, cadmium, silver, tin, lead and gold.  
     
     
         39 . The interposer substrate of  claim 29 , wherein at least one of the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprises multiple layers of at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin, lead and gold.  
     
     
         40 . The interposer substrate of  claim 29 , wherein conductive bumps protruding from at least one of the first and second surfaces are partially received in through holes extending through the substantially planar body.  
     
     
         41 . The interposer substrate of  claim 40 , wherein at least some of the conductive bumps partially received within the through holes comprise preformed bumps.  
     
     
         42 . The interposer substrate of  claim 41 , wherein the preformed bumps comprise solder balls in contact with a conductive paste disposed within the through holes.  
     
     
         43 . A method of forming an interposer substrate having a first level interconnect and a second level interconnect, the method comprising: 
 providing a substantially planar interposer substrate body having a first surface and a second surface; and    simultaneously plating conductive bumps associated with the first surface in a pattern for the first level interconnect and plating conductive bumps associated with the second surface in a pattern for the second level interconnect.    
     
     
         44 . The method of  claim 43 , wherein providing comprises forming through holes in the interposer substrate body extending between the first surface and the second surface and plating conductive bumps associated with at least one of the first and second surfaces therein.  
     
     
         45 . The method of  claim 44 , wherein providing comprises forming conductive lines over at least one of the first surface and the second surface of the interposer substrate body and extending between at least one of the through holes and at least one of the conductive bumps.  
     
     
         46 . The method of  claim 43 , wherein simultaneously plating comprises at least one of an electrolytic plating process and an electroless plating process.  
     
     
         47 . The method of  claim 46 , wherein the simultaneously plating comprises plating the conductive bumps from conductive materials comprising at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin and gold.  
     
     
         48 . The method of  claim 46 , wherein the simultaneously plating comprises forming at least some of the conductive bumps from multiple layers of conductive materials comprising at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin, lead and gold.  
     
     
         49 . The method of  claim 43 , wherein the simultaneously plating comprises configuring the conductive bumps to respectively protrude from the first surface and the second surface of the interposer substrate body.  
     
     
         50 . The method of  claim 44 , further comprising disposing a preformed conductive element on at least some of the conductive bumps plated within a through hole to protrude from at least one of the first and second surfaces of the interposer substrate body.  
     
     
         51 . A method of assembling a semiconductor device assembly, the method comprising: 
 providing at least one semiconductor die having an active surface and a back surface, the active surface having bond pads thereon;    providing an interposer substrate having a first surface and a second surface with conductive bumps protruding from the first surface of the interposer substrate and conductive bumps protruding from the second surface of the interposer substrate; and    electrically connecting the bond pads of the at least one semiconductor die to the conductive bumps protruding from the first surface of the interposer substrate.    
     
     
         52 . The method of  claim 51 , further comprising disposing a dielectric filler material between the at least one semiconductor die and the interposer substrate.  
     
     
         53 . The method of  claim 52 , wherein the disposing comprises dispensing the dielectric filler material in flowable form to fill a gap between the at least one semiconductor die and the interposer substrate.  
     
     
         54 . The method of  claim 52 , wherein the disposing comprises disposing a non-flowable dielectric filler material between the at least one semiconductor die and the interposer substrate.  
     
     
         55 . The method of  claim 54 , further comprising selecting the non-flowable dielectric filler material from the group consisting of a nonconductive film and an anisotropically conductive film.  
     
     
         56 . The method of  claim 51 , wherein the providing the at least one semiconductor die comprises providing a plurality of semiconductor dice.  
     
     
         57 . The method of  claim 51 , further comprising encapsulating the back surface of the at least one semiconductor die with an encapsulation material.  
     
     
         58 . An electronic system comprising: 
 a processor device coupled to an input device and an output device; and    a semiconductor device assembly coupled to at least one of the processor device, the input device and the output device, the semiconductor device assembly comprising: 
 at least one semiconductor die having an active surface and a back surface, the active surface having bond pads thereon; and  
 an interposer substrate having a first surface having conductive bumps protruding therefrom and a second surface, the bumps protruding from the first surface bonded to the bond pads on the active surface of the at least one semiconductor die.  
   
     
     
         59 . The system of  claim 58 , further comprising a dielectric filler material disposed between the at least one semiconductor die and the interposer substrate.  
     
     
         60 . The system of  claim 59 , wherein the dielectric filler material comprises one of a flowable material and a non-flowable material.  
     
     
         61 . The system of  claim 58 , further comprising an encapsulation material formed over the back surface of the at least one semiconductor die.  
     
     
         62 . The system of  claim 58 , wherein the interposer substrate comprises a plurality of through holes extending between the first surface and the second surface with conductive bumps positioned in through holes of the plurality and protruding from the second surface of the interposer substrate.  
     
     
         63 . The system of  claim 62 , further comprising at least one conductive line on the first surface of the interposer substrate, the at least one conductive line extending between at least one of the plurality of through holes and operably coupled with a conductive bump positioned therein and at least one of the conductive bumps protruding from the first surface.  
     
     
         64 . The system of  claim 62 , wherein the conductive bumps positioned in the through holes are preformed prior to positioning.  
     
     
         65 . The system of  claim 62 , wherein the conductive bumps protruding from the second surface are arranged to correspond to a pattern of terminal pads on another substrate.  
     
     
         66 . The system of  claim 58 , wherein the interposer substrate comprises a flexible material.  
     
     
         67 . The system of  claim 58 , wherein the interposer substrate comprises a polymeric material.  
     
     
         68 . The system of  claim 62 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise plated masses of metal.  
     
     
         69 . The system of  claim 62 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin, lead and gold.  
     
     
         70 . The system of  claim 62 , wherein at least one of the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprises multiple layers of at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin lead and gold.  
     
     
         71 . The system of  claim 62 , wherein the conductive bumps protruding from the second surface comprise preformed conductive bumps disposed on a conductive paste within the through holes.  
     
     
         72 . The system of  claim 62 , wherein the interposer substrate comprises multiple layers of conductive interconnect lines therein.  
     
     
         73 . The system of  claim 58 , wherein the at least one semiconductor die comprises a plurality of semiconductor dice.  
     
     
         74 . The system of  claim 58 , wherein the conductive bumps protruding from the first surface are bonded to the bond pads of the at least one semiconductor die through an anisotropically conductive film.  
     
     
         75 . The system of  claim 58 , wherein the interposer substrate comprises a plurality of through holes extending between the first surface and the second surface and at least some conductive bumps protruding from the first surface are positioned in through holes of the plurality.  
     
     
         76 . The system of  claim 75 , further comprising at least one conductive line on the second surface of the interposer substrate, the at least one conductive line extending between at least one of the plurality of through holes and operably coupled with a conductive bump positioned therein and at least one conductive bump protruding from the second surface.  
     
     
         77 . The system of  claim 75 , wherein the conductive bumps positioned in the through holes are preformed prior to positioning.  
     
     
         78 . The system of  claim 75 , wherein the conductive bumps protruding from the first surface comprise preformed conductive bumps disposed on a conductive paste within the through holes.  
     
     
         79 . The system of  claim 58 , further comprising conductive bumps protruding from the second surface and operably coupled to conductive bumps protruding from the first surface.  
     
     
         80 . The system of  claim 79 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface are operably coupled in part with through holes extending at least partially through the interposer substrate.  
     
     
         81 . The system of  claim 80 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface are operably coupled in part with conductive lines extending over at least one of the first and second surfaces.  
     
     
         82 . The system of  claim 79 , wherein the conductive bumps protruding from the first and second surfaces are formed, at least in part, of a common conductive material.  
     
     
         83 . The system of  claim 79 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise plated masses of metal.  
     
     
         84 . The system of  claim 79 , wherein the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprise at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin, lead and gold.  
     
     
         85 . The system of  claim 79 , wherein at least one of the conductive bumps protruding from the first surface and the conductive bumps protruding from the second surface comprises multiple layers of at least one of copper, nickel, chromium, zinc, brass, cadmium, silver, tin lead and gold.