Atomic layer deposition of CMOS gates with variable work functions

Abstract

Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition.

What is claimed is:  
     
         1 . A transistor, comprising: 
 a first source/drain region    a second source/drain region    a channel region between the first and the second source/drain regions,    a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition.    
     
     
         2 . The transistor of  claim 1 , wherein the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).  
     
     
         3 . The transistor of  claim 1 , wherein the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).  
     
     
         4 . The transistor of  claim 1 , wherein the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN).  
     
     
         5 . The transistor of  claim 1 , wherein the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).  
     
     
         6 . The transistor of  claim 1 , wherein the gate further includes a refractory metal formed on the ternary metallic conductor.  
     
     
         7 . A vertical multistate cell, comprising: 
 a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;    a sourceline coupled to the source region; and    a transmission line coupled to the drain region.    
     
     
         8 . The vertical multistate cell of  claim 7 , wherein the gate further includes a highly conductive polysilicon layer formed on the ternary metallic conductor.  
     
     
         9 . The vertical multistate cell of  claim 7 , wherein the gate further includes a refractory metal formed on the ternary metallic conductor.  
     
     
         10 . The vertical multistate cell of  claim 9 , wherein the refractory metal includes tungsten (W).  
     
     
         11 . The vertical multistate cell of  claim 9 , wherein the refractory metal includes tantalum (Ta).  
     
     
         12 . The vertical multistate cell of  claim 9 , wherein the refractory metal includes titanium (Ti).  
     
     
         13 . A vertical multistate cell, comprising: 
 a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Tantalum Aluminum Nitride (TaAlN) layer;    a wordline coupled to the gate;    a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and    a bit line coupled to the drain region.    
     
     
         14 . The vertical multistate cell of  claim 13 , wherein the gate further includes a refractory metal formed on the Tantalum Aluminum Nitride (TaAlN) layer.  
     
     
         15 . The vertical multistate cell of  claim 13 , wherein the refractory metal includes tantalum (Ta).  
     
     
         16 . The vertical multistate cell of  claim 13 , wherein the Tantalum Aluminum Nitride (TaAlN) layer is formed by atomic layer deposition.  
     
     
         17 . A vertical multistate cell, comprising: 
 a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Titanium Aluminum Nitride (TiAlN) layer;    a wordline coupled to the gate;    a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and    a bit line coupled to the drain region.    
     
     
         18 . The vertical multistate cell of  claim 17 , wherein the gate further includes a refractory metal formed on the Titanium Aluminum Nitride (TiAlN) layer.  
     
     
         19 . The vertical multistate cell of  claim 17 , wherein the refractory metal includes titanium (Ti).  
     
     
         20 . The vertical multistate cell of  claim 13 , wherein the Titanium Aluminum Nitride (TiAlN) layer is formed by atomic layer deposition.  
     
     
         21 . A vertical multistate cell, comprising: 
 a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Titanium Silicon Nitride (TiSiN) layer;    a wordline coupled to the gate;    a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and    a bit line coupled to the drain region.    
     
     
         22 . The vertical multistate cell of  claim 21 , wherein the gate further includes a refractory metal formed on the Titanium Silicon Nitride (TiSiN) layer.  
     
     
         23 . The vertical multistate cell of  claim 21 , wherein the refractory metal includes titanium (Ti).  
     
     
         24 . The vertical multistate cell of  claim 21 , wherein the Titanium Silicon Nitride (TiSiN) layer is formed by atomic layer deposition.  
     
     
         25 . A vertical multistate cell, comprising: 
 a vertical transistor extending outwardly from a substrate, the transistor having a source region, a drain region, a channel region between the source region and the drain region, a gate separated from the channel region by a gate oxide, wherein the gate includes a Tungsten Aluminum Nitride (WAlN) layer;    a wordline coupled to the gate;    a sourceline formed in a trench adjacent to the vertical transistor, wherein the source region is coupled to the sourceline; and    a bit line coupled to the drain region.    
     
     
         26 . The vertical multistate cell of  claim 25 , wherein the gate further includes a refractory metal formed on the Tungsten Aluminum Nitride (WAlN) layer.  
     
     
         27 . The vertical multistate cell of  claim 25 , wherein the refractory metal includes tungsten (W).  
     
     
         28 . The vertical multistate cell of  claim 25 , wherein the Tungsten Aluminum Nitride (WAlN) layer is formed by atomic layer deposition.  
     
     
         29 . A transistor array, comprising: 
 a number of transistor cells formed on a substrate, wherein each transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;    a number of bit lines coupled to the drain region of each transistor cell along rows of the transistor array;    a number of word lines coupled to the gate of each transistor cell along columns of the memory array; and    a number of sourcelines, wherein the source region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells.    
     
     
         30 . The transistor array of  claim 29 , wherein the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).  
     
     
         31 . The transistor array of  claim 29 , wherein the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).  
     
     
         32 . The transistor array of  claim 29 , wherein the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN).  
     
     
         33 . The transistor array of  claim 29 , wherein the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).  
     
     
         34 . The transistor array of  claim 29 , wherein the gate further includes a refractory metal formed on the ternary metallic conductor.  
     
     
         35 . A semiconductor device, comprising: 
 a memory array, wherein the memory array includes a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as transistors including a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;    a number of bit lines coupled to the drain region of each transistor along rows of the memory array;    a number of word lines coupled to the gate of each transistor along columns of the memory array;    a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the source regions of each transistor along rows of pillars, wherein along columns of the pillars the source region of each transistor in column adjacent pillars couple to the sourceline in a shared trench;    a wordline address decoder coupled to the number of wordlines;    a bitline address decoder coupled to the number of bitlines; and    a sense amplifier coupled to the number of bitlines.    
     
     
         36 . The semiconductor device of  claim 35 , wherein the number of sourcelines formed in a bottom of the trenches between rows of the pillars include a doped region implanted in the bottom of the trench.  
     
     
         37 . The semiconductor device of  claim 35 , wherein the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).  
     
     
         38 . The semiconductor device of  claim 35 , wherein the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).  
     
     
         39 . The semiconductor device of  claim 35 , wherein the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN).  
     
     
         40 . The semiconductor device of  claim 35 , wherein the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).  
     
     
         41 . The semiconductor device of  claim 35 , wherein the gate further includes a refractory metal formed on the ternary metallic conductor.  
     
     
         42 . An electronic system, comprising: 
 a processor; and    a memory device coupled to the processor, wherein the memory device includes;    a memory array, wherein the memory array includes a number of transistor cells formed on a substrate, wherein each transistor cell includes a source region, a drain region, a channel region between the source and the drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate includes a ternary metallic conductor formed by atomic layer deposition;    a number of bit lines coupled to the drain region of each transistor cell along rows of the transistor array;    a number of word lines coupled to the gate of each transistor cell along columns of the memory array; and    a number of sourcelines, wherein the source region of each transistor cell is coupled to the number of sourcelines along rows of the transistor cells.    
     
     
         43 . The electronic system of  claim 42 , wherein the ternary metallic conductor includes Tantalum Aluminum Nitride (TaAlN).  
     
     
         44 . The electronic system of  claim 42 , wherein the ternary metallic conductor includes Titanium Aluminum Nitride (TiAlN).  
     
     
         45 . The electronic system of  claim 42 , wherein the ternary metallic conductor includes Titanium Silicon Nitride (TiSiN).  
     
     
         46 . The electronic system of  claim 42 , wherein the ternary metallic conductor includes Tungsten Aluminum Nitride (WAlN).  
     
     
         47 . The electronic system of  claim 42 , wherein the gate further includes a refractory metal formed on the ternary metallic conductor.  
     
     
         48 . A method for forming a transistor, comprising: 
 forming a first source/drain region, a second source/drain region, and a channel region therebetween in a substrate;    forming a gate opposing the channel region and separated therefrom by a first gate insulator; and    wherein forming the gate includes forming a ternary metallic conductor by atomic layer deposition.    
     
     
         49 . The method of  claim 48 , wherein forming a ternary metallic conductor by atomic layer deposition includes forming a Tantalum Aluminum Nitride (TaAlN) layer.  
     
     
         50 . The method of  claim 48 , wherein forming a ternary metallic conductor by atomic layer deposition includes forming a Titanium Aluminum Nitride (TiAlN) layer.  
     
     
         51 . The method of  claim 48 , wherein forming a ternary metallic conductor by atomic layer deposition includes forming a Titanium Silicon Nitride (TiSiN) layer.  
     
     
         52 . The method of  claim 48 , wherein forming a ternary metallic conductor by atomic layer deposition includes forming a Tungsten Aluminum Nitride (WAlN) layer.  
     
     
         53 . The method of  claim 48 , wherein method further includes forming a refractory metal on the ternary metallic conductor.  
     
     
         54 . A transistor pair, comprising: 
 a PMOS transistor;    an NMOS transistor;    wherein the NMOS and the PMOS transistor each include a source, a drain, a channel region therebetween, a gate separated from the channel region by a gate insulator; and    wherein the gates of the NMOS and the PMOS transistors include a varied composition and a varied work function to achieve a low threshold voltages of a same magnitude.    
     
     
         55 . The transistor pair of  claim 54 , wherein the low threshold voltages of a same magnitude include a threshold voltage magnitude of less than 0.4 Volts.  
     
     
         56 . The transistor pair of  claim 54 , wherein the low threshold voltages of a same magnitude include a threshold voltage magnitude of approximately 0.3 Volts.  
     
     
         57 . The transistor pair of  claim 54 , wherein one of the gates of the NMOS and the PMOS transistors includes a binary metallic conductor and the other includes a ternary metallic conductor.  
     
     
         58 . The transistor pair of  claim 57 , wherein the binary metallic conductor includes a binary metallic conductor selected from the group of tantalum nitride (TaN), titanium nitride (TiN), and tungsten nitride (WN).  
     
     
         59 . A method for forming a transistor pair, comprising: 
 forming a PMOS transistor;    forming an NMOS transistor; and    wherein forming the NMOS and the PMOS transistors includes forming a varied gate composition having a varied work function on each respective transistor in order to control a threshold voltage for each respective transistor to a same magnitude.