Devices and methods for controlling active termination resistors in a memory system

Abstract

A termination resistor is mounted on a memory circuit and provides a termination resistance for the memory circuit. The termination resistor includes a node, a plurality of first termination resistors responsive to a corresponding control signal and connected between a power voltage and the node, and a plurality of second termination resistors responsive to a corresponding control signal and connected between a ground voltage and the node.

What is claimed is:  
     
         1 . A termination resistor which is mounted on a memory circuit so as to provide a termination resistance for the memory circuit, and which comprises: 
 a node;    a plurality of first termination resistors responsive to a first control signal and connected between a first reference voltage and the node; and    a plurality of second termination resistors responsive to a second control signal and connected between a second reference voltage and the node.    
     
     
         2 . The termination resistor of  claim 1 , wherein the plurality of first termination resistors are responsive to the first control signal to tune a resistance between the node and the first reference voltage.  
     
     
         3 . The termination resistor of  claim 1 , wherein the plurality of second termination resistors are responsive to the second control signal to tune a resistance between the node and the second reference voltage.  
     
     
         4 . The termination resistor of  claim 1 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.  
     
     
         5 . The termination resistor of  claim 2 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.  
     
     
         6 . The termination resistor of  claim 3 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.  
     
     
         7 . A termination resistor which is mounted on a memory circuit so as to provide a termination resistance for the memory circuit, and which comprises: 
 a node;    a first UP resistor connected between a first reference voltage and the node;    a second UP resistor responsive to a first control signal and connected between the first reference voltage and the node; and    a third UP resistor responsive to a second control signal and connected between the first reference voltage and the node.    
     
     
         8 . The termination resistor of  claim 7 , further comprising: 
 a first DOWN resistor connected between a second reference voltage and the node;    a second DOWN resistor responsive to a third control signal and connected between the second reference voltage and the node; and    a third DOWN resistor responsive to a fourth control signal and connected between the second reference voltage and the node.    
     
     
         9 . The termination resistor of  claim 8 , further comprising: 
 a first switching circuit which electrically couples the first reference voltage to the first UP resistor in response to an UP signal;    a second switching circuit which electrically couples the first reference voltage to the second UP resistor in response to the first control signal; and    a third switching circuit which electrically couples the first reference voltage to the third UP resistor in response to the second control signal.    
     
     
         10 . The termination resistor of  claim 9 , further comprising: 
 a fourth switching circuit which electrically couples the first DOWN resistor to the second reference voltage in response to a DOWN signal;    a fifth switching circuit which electrically couples the second DOWN resistor to the second reference voltage in response to the third control signal; and    a sixth switching circuit which electrically couples the third DOWN resistor to the second reference voltage in response to the fourth control signal.    
     
     
         11 . The termination resistor of  claim 10 , wherein the first through sixth switching circuits are MOS transistors.  
     
     
         12 . The termination resistor of  claim 7 , wherein the first reference voltage is a power supply voltage.  
     
     
         13 . The termination resistor of  claim 8 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.  
     
     
         14 . The termination resistor of  claim 9 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.  
     
     
         15 . The termination resistor of  claim 10 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.  
     
     
         16 . The termination resistor of  claim 11 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.  
     
     
         17 . A method for tuning a resistance of a terminal resistor mounted on a memory circuit so as to provide a termination resistance for the memory circuit, the method comprising: 
 measuring, in response to a first control signal, a resistance of at least one of a plurality of first termination resistors which are connected between a first reference voltage and a node;    adjusting, in response to a second control signal and according to the measured resistance of the at least one of the plurality of first termination resistors, the number of first termination resistors electrically coupled between the first reference voltage and the node.    
     
     
         18 . The method of  claim 17 , further comprising: 
 measuring, in response to a third control signal, a resistance of at least one of a plurality of second termination resistors which are connected between a second reference voltage and the node;    adjusting, in response to a fourth control signal and according to the measured resistance of the at least one of the plurality of second termination resistors, the number of second termination resistors electrically coupled between the second reference voltage and the node.    
     
     
         19 . The termination resistor of  claim 17 , wherein the first reference voltage is a power supply voltage.  
     
     
         20 . The termination resistor of  claim 18 , wherein the first reference voltage is a power supply voltage and the second reference voltage is a ground voltage.