Reshuffled communications processes in pipelined asynchronous circuits

Abstract

An asynchronous processor that has reshuffled processes to implement precharge logic.

What is claimed is:  
     
         1 . An asynchronous circuit, comprising: 
 a first process;    a second process, communicating with said first process;    wherein said first and second processes communicate using precharge logic that receive inputs in a first gate, and test nuetrality of said inputs in a second gate separate from said first gate.    
     
     
         2 . A circuit as in  claim 1  where each of said first and second processes communicate via request and acknowledges.  
     
     
         3 . A circuit as in  claim 1  further comprising determining a specified request, setting a state variable to represent said specified request, and resetting said specified request before acknowledging or acting on it.  
     
     
         4 . A circuit as in  claim 1  wherein said first and second processes communicate according to 
 PCFB≡*[[ R a {circumflex over ( )}L]; R↑; L a ↑; en↓([R a ]; R↓), [ L]; L a ↓); en↑.  
 
     
     
         5 . A circuit as in  claim 1  wherein said first and second processses communicate according to 
 PCHB≡*[[ R a {circumflex over ( )}L]; R↑; L a ↑; [R a ]; R↓; [ L]; L a ↓.  
 
     
     
         6 . A circuit according to  claim 1  wherein said precharge logic includes a first portion which computes validity of inputs and a second portion which computes validity of outputs.  
     
     
         7 . A method of communicating between first and second processes without a synchronizing global clock, comprising: 
 receiving requests in a first gate; and    acknowledging said requests prior to completion of action thereon, and    determining neutrality of said inputs in a second gate that is separate from said first gate that receives the input.    
     
     
         8 . A method as in  claim 7  wherein said device set test validity of the input using at least one transistor which is unconnected to the transistor of the device that receives the inputs.  
     
     
         9 . A method of operating an asynchronous process, comprising: 
 receiving a request for some action to occur;    reshuffling responses that usually occur relative to said request, said reshuffling responses including using a precharge logic.    
     
     
         10 . A cell, comprising: 
 a buffering element;    a logic element, connected to said buffering element, said logic element having a dual rail precharge domino logic block which computes an output based on an input;    a completion tree for an input channel and a completion tree for an output channel; and    a control circuit which combines the completion trees to generate an input acknowledge and to precharge the logic element.    
     
     
         11 . A cell as in  claim 10 , wherein said input acknowledge does not wait for nuetrality of output data, and also producing an enable which does wait for nuetrality of output data.  
     
     
         12 . A cell as in  claim 10 , wherein said outputs are conditionally produced by indicating a condition with an extra wire.  
     
     
         13 . A cell as in  claim 10 , wherein said inputs are conditional inputs  
     
     
         14 . A cell as in  claim 10 , wherein said input is only conditionally acknowledged, and said logic determines which inputs to acknowledge.