Fabrication of nanoelectronic circuits

Abstract

A silicon substrate is coated with one or more layers of resist. First and second circuit patterns are exposed in sequence, where the second pattern crosses the first pattern. The patterned resist layers are developed to open holes which extend down to the substrate only where the patterns cross over each other. These holes provide a mask suitable for implanting single phosphorous ions in the substrate, for a solid state quantum computer. Further development of the resist layers provides a mask for the deposition of nanoelectronic circuits, such as single electron transistors, aligned to the phosphorous ions.

1 . (amended) A method for fabricating nanoelectronic circuits, including the steps of: 
 coating a semiconductor substrate with one or more layers of resist;    exposing a first circuit pattern into the one or more layers of resist;    exposing a second circuit pattern into the resist layers, such that this pattern crosses the previously exposed pattern;    developing the patterned resist layers to open holes through them which extend down to the semiconductor substrate surface only where the patterns cross over each other; and    implanting an ion through each hole.    
     
     
         2 . A method according to  claim 1 , where the step of exposing a first circuit pattern is followed by development of this pattern.  
     
     
         3 . A method according to  claim 1 , where the step of exposing a first circuit pattern is followed by coating with one or more additional layers of resist.  
     
     
         4 . (deleted)  
     
     
         5 . A method according to any preceding claim, including the further step of further developing the patterned resist layers to open further areas of the semiconductor substrate surface around the holes.  
     
     
         6 . A method according to any preceding claim, including the further step of evaporating metal at different angles through remaining resist layers to create active devices and conducting control gates on the semiconductor substrate surface positioned relative to the implanted ions as determined by the angle of evaporation.  
     
     
         7 . A method according to any preceding claim, where one circuit pattern defines the geometry of active devices and conducting control gates, and another circuit pattern defines the locus on which the holes are to be opened for the ion implantation.  
     
     
         8 . A method according to any preceding claim, where both circuit patterns are written with the same resolution and accuracy as each other.  
     
     
         9 . A method according to  claim 7  or  claim 7  and  8 , where part of the complex pattern for the active devices and conducting gates is a series of parallel straight lines and the other pattern is a straight line transverse to the straight lines of the other pattern.  
     
     
         10 . A method of fabricating nanoelectronic circuits suitable for solid state quantum computer control and read-out, according to  claim 6 , utilising a multi-layer resist through which one or more ions are implanted through each hole, and a multi-angle metal deposition used to create the active devices and the control gates registered above the implanted ions.  
     
     
         11 . A method of fabricating nanoelectronic circuits suitable for solid state quantum computer control and read-out, according to  claim 6  or  claim 10 , in which a three-layer resist is used, and a double-angle or triple-angle metal deposition is used.  
     
     
         12 . A method according to  claim 10  or  claim 11 , comprising the steps of: 
 coating a semiconductor substrate with a first resist;  
 writing a first pattern for the locus of ion positions into the first resist;  
 developing the first pattern;  
 coating with a second resist and then with a third resist of lower sensitivity than the second resist, where both the second and third resist use a different developer process to the first resist;  
 writing a second pattern for the metal circuitry into the resist layers such that the second pattern crosses over the first pattern;  
 partially developing the second pattern, such that trenches are opened in the second and third resists only where the second pattern is defined, and such that holes down to the silicon substrate are opened only where the first and second patterns cross each other.  
 
     
     
         13 . A method according to  claim 12 , comprising the additional step of: 
 implanting single ions through each hole;    
     
     
         14 . A method according to  claim 13 , comprising the additional step of: 
 fully developing the second pattern to create a cavity region under the third resist.    
     
     
         15 . A method according to  claim 14 , comprising the additional step of: 
 removing the remainder of the first resist which lies within the cavity.    
     
     
         16 . A method according to  claim 15 , comprising the additional step of: 
 evaporating metal at a first angle through the resist layers.    
     
     
         17 . A method according to  claim 16 , comprising the additional step of: 
 oxidising the surface of the first metal layer.    
     
     
         18 . A method according to  claim 17 , comprising the additional step of: 
 evaporating metal at a second angle through the resist layers.    
     
     
         19 . A method according to  claim 18 , comprising the additional step of: 
 evaporating metal at a third angle through the resist layers.    
     
     
         20 . A method according to  claim 19 , comprising the additional step of: 
 lifting-off all resist layers in solvents to reveal a completed device.    
     
     
         21 . A method according to  claim 20 , comprising the additional step of: 
 passivating or glassivating the surface as required.    
     
     
         22 . A method according to  claim 21 , comprising the additional step of: 
 annealing the sample to activate the dopants and remove ion-beam damage.    
     
     
         23 . A nanoelectronic circuit fabricated according to the method of any preceding claim.