Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device of a low power consumption capable of performing under a low voltage has an array section 21 in which only low threshold voltage MOS FETs are formed, and areas other than the array section 21 in which high threshold voltage MOS FETs whose threshold voltage is higher than that of each low threshold voltage MOS FET formed in the array section are formed.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device comprising: 
 an internal circuit section in which an integrated circuit is formed, the integrated circuit including at least MOS transistors of same conductivity type,    a plurality of terminal pads including signal pads,    a plurality of buffer regions connected to said signal pads, respectively,    each buffer region including at least one of an input buffer circuit and an output buffer circuit, the input buffer circuit connected between the internal circuit and one of the signal pads and transfers a signal from the one signal pad to the internal circuit, and the output buffer circuit connected between the internal circuit and the one signal pad and transfers a signal from the internal circuit to the one signal pad, and    a space region defined by one corner of said internal circuit section, a first hypothetical line extends from a first side as a boundary of said internal circuit section from the one corner, and a second hypothetical line extends from a second side as a boundary of said internal circuit section from the one corner, said second hypothetical line being orthogonal with said first side at the one corner,    wherein a MOS transistor, having a threshold voltage whose absolute value is higher than that of each of the MOS transistors in said internal circuit section, is formed in said space region.    
     
     
         2 . A semiconductor integrated circuit device comprising: 
 an internal circuit section in which an integrated circuit is formed, the integrated circuit including at least MOS transistors of same conductivity type,    a plurality of terminal pads including signal pads,    a plurality of buffer circuits connected to said signal pads, respectively,    each buffer circuit including at least one of an input buffer circuit and an output buffer circuit, the input buffer circuit connected between the internal circuit and one of the signal pads and transfers a signal from the one signal pad to the internal circuit, and the output buffer circuit connected between the internal circuit and the one signal pad and transfers a signal from the internal circuit to the one signal pad, and    four space regions corresponding to four different corners of the internal circuit section, respectively, each space region defined by one corner of the four, a first hypothetical line extends from a first side as a boundary of said internal circuit section from the one corner, and a second hypothetical line extends from a second side as a boundary of said internal circuit section from the one corner, said second hypothetical line being orthogonal with said first side at the one corner,    wherein a MOS transistor, having a threshold voltage whose absolute value is higher than that of each of the MOS transistors in said internal circuit section, is formed in each space region.    
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , wherein the MOS transistor formed at the one space region is a switch which supplies an electrical power to the internal circuit from a power source pad.  
     
     
         4 . The semiconductor integrated circuit device according to  claim 2 , wherein the MOS transistor formed at each space region is a switch which supplies an electrical power to the internal circuit from a power source pad.  
     
     
         5 . A semiconductor integrated circuit device comprising: 
 an internal circuit section in which an integrated circuit is formed, the integrated circuit including at least MOS transistors of same conductivity type,    a plurality of input/output circuit regions arranged opposite to four sides of said internal circuit section, respectively, each input/output circuit region including a plurality of buffer circuits connected to the signal pads, respectively,    each buffer circuit including at least one of an input buffer circuit and an output buffer circuit, the input buffer circuit connected between the internal circuit and one of the signal pads and transfers a signal from the one signal pad to the internal circuit, and the output buffer circuit connected between the internal circuit and the one signal pad and transfers a signal from the internal circuit to the one signal pad; and    MOS transistors having threshold voltages whose absolute values are higher than that of each of the MOS transistors in said internal circuit section, and arranged between said internal circuit section and said plurality of input/output circuit regions and in a loop surrounding said internal circuit section.    
     
     
         6 . The semiconductor integrated circuit device according to  claim 5 , wherein the MOS transistor formed in the space region is a switch which supplies an electrical power to the internal circuit from a power source pad.