SOI voltage-tolerant body-coupled pass transistor

Abstract

A method and device for A pass transistor device which includes a source; a drain opposite the source, a body between the source and the drain, and a circuit control network connected between the drain and the source, wherein the circuit control network controls a potential voltage of the body and provides overvoltage protection to the pass transistor.

What is claimed is:  
     
         1 . A pass transistor device comprising: 
 a source;    a drain opposite said source;    a body between said source and said drain; and    a circuit control network connected between said drain and said source, said circuit control network controlling a potential voltage of said body and providing overvoltage protection to said pass transistor.    
     
     
         2 . The device in  claim 1 , wherein said circuit control network comprises a body-charging element.  
     
     
         3 . The device in  claim 2 , wherein said body-charging element comprises a Lubistor.  
     
     
         4 . The device in  claim 2 , wherein said body-charging element comprises a body- and gate-coupled silicon over insulator (SOI) diode element.  
     
     
         5 . The device in  claim 2 , wherein said body-charging element comprises at least one Lubistor.  
     
     
         6 . The device in  claim 2 , wherein said body-charging element comprises a silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET).  
     
     
         7 . The device in  claim 2 , wherein said body-charging element comprises a body- and gate-coupled silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET) diode.  
     
     
         8 . The device in  claim 1 , wherein said circuit control network comprises a body-limiting element.  
     
     
         9 . The device in  claim 1 , wherein said circuit control network comprises a voltage divider network.  
     
     
         10 . The device in  claim 9 , wherein said voltage divider includes at least one resistor.  
     
     
         11 . The device in  claim 10 , wherein said resistor comprises a buried resistor element.  
     
     
         12 . The device in  claim 10 , wherein the resistor comprises a silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET).  
     
     
         13 . The device in  claim 1 , wherein said circuit control network comprises at least one resistor-capacitor series configured element whose center node is connected to said SOI body of said pass transistor.  
     
     
         14 . A silicon over insulator (SOI) metal oxide silicon field effect transistor (MOSFET) device comprising: 
 a body;    a gate opposite said body;    a resistive/capacitor discriminator connected to said gate; and    a circuit control network connected to said body, said circuit control network modulating a potential voltage of said body to provide electrostatic discharge (ESD) protection.    
     
     
         15 . The device in  claim 14 , wherein said control circuit is connected to said gate.  
     
     
         16 . The device in  claim 14 , wherein said control network circuit modulates said potential voltage of said body.  
     
     
         17 . The device in  claim 14 , wherein said control network circuit limits said body to a reference voltage.  
     
     
         18 . The device in  claim 14 , wherein said control circuit comprises at least one SOI MOSFET.  
     
     
         19 . The device in  claim 14 , wherein said control network comprises at least one ESD SOI diode.  
     
     
         20 . The device in  claim 14 , wherein said control network circuit comprises at least one body/gate-coupled SOI diode.  
     
     
         21 . The device in  claim 14 , wherein said control network comprises n-channel and p-channel SOI MOSFETs, at least two RC discriminators and at least one control circuit network.  
     
     
         22 . The device in  claim 14 , further comprising: 
 an input pad connected to said gate;    a drain adjacent said gate: and    a source opposite said drain,    wherein said control network is connected to said input pad and said drain and said source is connected to Vss.