DRAM semiconductor device and method for fabricating the same

Abstract

Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

What is claimed is:  
     
         1 . A DRAM semiconductor device comprising: 
 a gate stack pattern formed on a semiconductor substrate:    a source/drain region which is aligned with both sidewalls of the gate stack pattern and formed on the semiconductor substrate;    a gate spacer formed on both sidewalls of the gate stack pattern;    a silicon epitaxial layer formed on the source/drain region on both sides of the gate spacer;    a metal silicide layer formed on the silicon epitaxial layer; and    a metal pad formed on the metal silicide layer.    
     
     
         2 . The DRAM semiconductor device of  claim 1 , wherein the metal pad is level with or higher than the gate stack pattern.  
     
     
         3 . The DRAM semiconductor device of  claim 1 , wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.  
     
     
         4 . The DRAM semiconductor device of  claim 1 , wherein the metal pad is constructed with a tungsten film.  
     
     
         5 . The DRAM semiconductor device of  claim 1 , wherein the source/drain region is an n− source/drain region.  
     
     
         6 . A DRAM semiconductor device comprising: 
 a gate stack pattern formed on a cell region and a peripheral circuit region of a semiconductor substrate;    a n− source/drain region which is aligned with both sidewalls of the gate stack pattern of the cell region and formed on the semiconductor substrate;    a n+ source/drain region and a p+ source/drain region which is aligned with both sidewalls of the gate stack pattern of the peripheral circuit region and formed on the semiconductor substrate;    a gate spacer formed on both sidewalls of the gate stack pattern of the cell region and the peripheral circuit region;    a silicon epitaxial layer formed on the n− source/drain region, the n+ source/drain region and the p+ source/drain region of a lower portion of both sides of the gate spacer;    a metal suicide layer formed on the silicon epitaxial layer of the cell region and the peripheral circuit region;    a metal pad formed on the metal silicide layer of the cell region; and    a metal plug formed on the metal silicide layer of the peripheral circuit region.    
     
     
         7 . The DRAM semiconductor device of  claim 6 , wherein the metal pad is level with equivalent to or higher than the gate stack pattern.  
     
     
         8 . The DRAM semiconductor device of  claim 6 , wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.  
     
     
         9 . The DRAM semiconductor device of  claim 6 , wherein the metal pad and the metal plug are constructed with a tungsten film.  
     
     
         10 . A method for fabricating a DRAM semiconductor device, the method comprising: 
 forming a gate stack pattern on a semiconductor substrate;    forming a source/drain region on the semiconductor substrate, which is aligned with both sidewalls of the gate stack pattern;    forming a silicon epitaxial layer on the source/drain region of both sidewalls of the gate spacer;    forming a metal silicide layer on the silicon epitaxial layer; and    forming a metal pad on the metal silicide layer.    
     
     
         11 . The method of  claim 10 , wherein the metal pad is level with or higher than the gate stack pattern.  
     
     
         12 . The method of  claim 10 , wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.  
     
     
         13 . The method of  claim 10 , wherein the metal pad and the metal plug are constructed with a tungsten film.  
     
     
         14 . The method of  claim 10 , wherein the source/drain region is an n− source/drain region.  
     
     
         15 . The method of  claim 10 , the silicon epitaxial layer is formed by using selective epitaxial growth.  
     
     
         16 . A method for fabricating a DRAM semiconductor device, the method comprising: 
 forming a gate stack pattern on a cell region and a peripheral circuit region of a semiconductor substrate;    forming a n− source/drain region on the semiconductor substrate of the cell region, to be aligned with both sidewalls of the gate stack pattern of the cell region, and forming a n+ source/drain region and a p+ source/drain region on the semiconductor substrate of the peripheral circuit region;    forming a gate spacer on both sidewalls of the gate stack pattern of the cell region and the peripheral circuit region;    forming a silicon epitaxial layer on the n− source/drain region, the n+ source/drain region and the p+ source/drain region of a lower portion of both sides of the gate spacer;    forming a metal silicide layer on the silicon epitaxial layer of the cell region and the peripheral circuit region;    forming a metal pad on the metal silicide layer of the cell region; and    forming a metal plug on the metal silicide layer of the peripheral circuit region.    
     
     
         17 . The method of  claim 16 , wherein the metal pad is level with or higher than the gate stack pattern.  
     
     
         18 . The method of  claim 16 , wherein the metal silicide layer is one of a cobalt silicide layer, a titanium silicide layer and a nickel silicide layer.  
     
     
         19 . The method of  claim 16 , wherein the metal pad and the metal plug are a tungsten film.  
     
     
         20 . The method of  claim 16 , the silicon epitaxial layer is formed by using selective epitaxial growth.