Silicon on isulator (SOI) transistor and methods of fabrication

Abstract

The present invention is a silicon on insulator (SOI) transistor and its method of fabrication. According to the present invention, an opening is formed in the insulating layer formed on a single crystalline silicon substrate. An amorphous or polycrystalline silicon or silicon alloy is then formed in the opening on the single crystalline silicon substrate and on the insulating layer. The amorphous or polycrystalline silicon or silicon alloy in the opening and at least a portion of the amorphous or polycrystalline silicon or silicon alloy on the insulating layer is crystallized into a single crystalline silicon or silicon alloy film.

We claim:  
     
         1 . A semiconductor device comprising: 
 a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon film having a single crystalline silicon or silicon alloy portion;    a gate dielectric on said single crystalline silicon portion of said silicon film;    a gate electrode on said gate dielectric;    a source and a drain region formed on opposite sides of said gate electrode in said silicon or silicon alloy film; and    a single crystalline silicon or silicon alloy window portion extending from said single crystalline silicon substrate through an opening in said insulating layer to said single crystalline silicon or silicon alloy portion of said silicon film.    
     
     
         2 . The semiconductor device of  claim 1  wherein said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film has a thickness of less than 30 nanometers.  
     
     
         3 . The semiconductor device of  claim 1  wherein said single crystalline silicon window portion forms part of said source region.  
     
     
         4 . The semiconductor device of  claim 1  wherein said silicon or silicon alloy film further includes a polysilicon or an amorphous silicon or silicon alloy portion.  
     
     
         5 . The semiconductor device of  claim 4  wherein said polysilicon or amorphous silicon or silicon alloy portion forms part of said drain region.  
     
     
         6 . A semiconductor device comprising: 
 a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon or silicon alloy film having a single crystalline silicon or silicon alloy portion having a thickness of less than or equal to 30 nanometers;    a gate dielectric on said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film;    a gate electrode on said gate dielectric; and    a source region and a drain region in said silicon or silicon alloy film on opposite sides of said gate electrode.    
     
     
         7 . The semiconductor device of  claim 6  wherein in said silicon or silicon alloy film further comprises an amorphous or polycrystalline portion.  
     
     
         8 . The semiconductor device of  claim 7  wherein said amorphous or polycrystalline portion forms part of said drain region.  
     
     
         9 . The semiconductor device of  claim 7  further comprising a single crystalline silicon or silicon alloy window portion extending from said single crystalline silicon substrate through an opening in said insulating layer to said single crystalline silicon or silicon alloy portion of said silicon or silicon alloy film.  
     
     
         10 . The semiconductor device of  claim 9  wherein said single crystalline silicon or silicon alloy window portion forms part of said source region.  
     
     
         11 . A semiconductor device comprising: 
 a silicon or silicon alloy film formed on an insulating layer formed on a single crystalline silicon substrate, said silicon or silicon alloy film having a single crystalline silicon or silicon alloy portion and an amorphous or polycrystalline portion;    a gate dielectric on said single crystalline silicon or silicon alloy portion;    a gate electrode on said gate dielectric; and    a source and a drain region in said silicon or silicon alloy film on opposite sides of said gate electrode.    
     
     
         12 . The semiconductor device of  claim 6  further comprising a polish stop layer on said insulating layer adjacent to said silicon film.  
     
     
         13 . The semiconductor device of  claim 11  wherein said polish stop layer is selected from the group consisting of silicon nitride and silicon carbide.  
     
     
         14 . A method of forming a semiconductor device comprising: 
 forming an opening in an insulating layer formed on a single crystalline silicon substrate;    forming an amorphous or polycrystalline silicon or silicon alloy layer in said opening on said single crystalline silicon substrate and on said insulating layer; and    crystallizing said amorphous or polycrystalline silicon or silicon alloy film in said opening and a least a portion of said amorphous or polycrystalline silicon or silicon alloy film formed on said insulating layer into a single crystalline silicon or silicon alloy film.    
     
     
         15 . The method of  claim 14  further comprising forming a gate dielectric layer on said single crystalline silicon or silicon alloy portion on said insulating layer; and 
 forming a gate electrode on said gate dielectric.  
 
     
     
         16 . The method of  claim 14  wherein the length of said crystallized portion of said single crystalline silicon or silicon alloy film on said insulating layer is greater than 1.0 micron.  
     
     
         17 . The method of  claim 14  further comprising forming a dielectric capping layer on said amorphous or polycrystalline silicon or silicon alloy film prior to crystallizing said amorphous or polycrystalline silicon or silicon alloy film.  
     
     
         18 . The method of  claim 14  further comprising forming a source region and a drain region on opposite sides of said gate electrode in said silicon or silicon alloy film.  
     
     
         19 . The method of  claim 18  wherein said source region includes said single crystalline silicon or silicon alloy film in said opening.  
     
     
         20 . The method of  claim 18  wherein said drain region includes a single crystalline silicon or silicon alloy portion and a amorphous or polycrystalline silicon or silicon alloy portion.  
     
     
         21 . The method of  claim 14  wherein said amorphous or polycrystalline silicon or silicon alloy film is formed to a thickness less than 30 nanometers.  
     
     
         22 . The method of  claim 14  wherein said crystallization step comprises a laser anneal.  
     
     
         23 . The method of  claim 14  wherein said crystallization step includes a high temperature anneal.  
     
     
         24 . A method of forming a semiconductor device comprising: 
 forming a polish stop layer on a insulating layer formed on a single crystalline silicon substrate;    forming an opening in said polish stop layer;    forming an opening in said insulating layer within said opening in said polish stop layer;    forming an amorphous or polycrystalline silicon or silicon alloy film in said opening on said single crystalline silicon substrate in said opening of said insulating layer, on said insulating layer within said opening in said polish stop layer, and on said polish stop layer;    crystallizing said amorphous or polycrystalline silicon or silicon alloy film in said opening in said insulating layer and at least a portion of said amorphous or polycrystalline silicon or silicon alloy film formed on said insulating layer within said polish stop layer into a single crystalline silicon or silicon alloy film; and    polishing said single crystalline silicon or silicon alloy film on said insulating layer until said single crystalline silicon or silicon alloy film is removed from said polish stop layer and is substantially planar with said polish stop layer.    
     
     
         25 . The method of  claim 24  further comprising forming a gate dielectric layer on said single crystalline silicon or silicon alloy portion on said insulating layer; and 
 forming a gate electrode on said gate dielectric.  
 
     
     
         26 . The method of  claim 24  wherein the length of said crystallized portion of said single crystalline silicon or silicon alloy film on said insulating layer is greater than 0.05 micron.  
     
     
         27 . The method of  claim 24  further comprising forming a dielectric capping layer on said amorphous or polycrystalline silicon or silicon alloy film prior to crystallizing said amorphous or polycrystalline silicon or silicon alloy film.  
     
     
         28 . The method of  claim 24  further comprising forming a source region and a drain region on opposite sides of said gate electrode in said silicon or silicon alloy film.  
     
     
         29 . The method of  claim 28  wherein said source region includes said single crystalline silicon or silicon alloy film in said opening.  
     
     
         30 . The method of  claim 28  wherein said drain region includes a single crystalline silicon or silicon alloy portion and a amorphous or polycrystalline silicon or silicon alloy portion.  
     
     
         31 . The method of  claim 24  wherein said amorphous or polycrystalline silicon or silicon alloy film is formed to a thickness greater than >100 nanometers.  
     
     
         32 . The method of  claim 24  wherein said crystallization step comprises a laser anneal.  
     
     
         33 . The method of  claim 24  wherein said crystallization step includes a high temperature anneal.  
     
     
         34 . The method of  claim 24  wherein said polish stop layer is selected from the group consisting of silicon nitride and silicon carbide or silicon oxide.