Microprocessor for executing byte compiled Java code

Abstract

A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.

1 . A microprocessor for executing byte compiled Java code in hardware comprising: 
 a RISC processor;    a Java module to execute a first set of Java instructions in the RISC processor;    a RISC module to execute a second set of Java instructions as microcode in the RISC processor, said RISC module including means for handling interrupts and a flexible hardware interface to control highly specialized peripheral devices; and    a datapath in the RISC processor shared by both modules, said datapath including a register file shared by both modules, said register file having a plurality of elements shared by the Java module and the RISC module, the Java module seeing a first portion of the plurality of elements as a circular Java operand stack and a remaining portion of the plurality of elements as storage registers, the RISC module seeing the plurality of elements as a register file.    
     
     
         2 . The microprocessor of  claim 1  wherein the register file includes a control bit for tracking which module is in operation.  
     
     
         3 . The microprocessor of  claim 1  wherein the register file includes a program counter containing the address of an instruction to be executed.  
     
     
         4 . The microprocessor of  claim 1  wherein the register file includes a program counter base register for storing the address of a new method to be invoked.  
     
     
         5 . The microprocessor of  claim 1  wherein the register file includes a local variable base address to store base address information for local variables in a Java method.  
     
     
         6 . The microprocessor of  claim 1  wherein the register file includes a Java stack pointer to track a location of the top of the Java operand stack.  
     
     
         7 . The microprocessor of  claim 1  wherein the register file includes a RISC stack pointer to point to a location where the RISC can temporarily store variables if the register file is full.  
     
     
         8 . The microprocessor of  claim 1  wherein the register file includes a status register having a pair of status bits that inform the RISC module to use a value of the top of the JAVA operand stack as a register operand when executing a Java instruction, each of the pair of status bits controlling an source or a destination operand.  
     
     
         9 . The microprocessor of  claim 8  wherein when the status bits are set, the RISC module disregards the source or destination operand and uses the contents of a predefined register as the source or destination operand.  
     
     
         10 . The microprocessor of  claim 8  wherein the status bits are set and cleared by a RISC program that replaces the Java instruction.  
     
     
         11 . The microprocessor of  claim 1  wherein the RISC processor has a SMILE RISC architecture.  
     
     
         12 . The microprocessor of  claim 1  wherein a control bit is located in a status register that is located outside of the register file.  
     
     
         13 . A microprocessor for executing byte compiled Java code in hardware comprising: 
 a RISC processor;    a Java module to execute a first set of Java instructions in the RISC processor;    a RISC module to execute a second set of Java instructions as microcode in the RISC processor, the second set of instructions being more complex than the first set of instructions, said RISC module including means for handling interrupts and a flexible hardware interface to control highly specialized peripheral devices; and    a datapath shared by both modules, said datapath including a register file shared by both modules, said register file including: 
 i) a plurality of elements shared by the Java module and the RISC module, the Java module seeing half of these elements as a circular Java operand stack and the other half as storage registers, the RISC module seeing the plurality of elements as a register file;  
 ii) a control bit tracking which module is in operation;  
 iii) a program counter containing the address of an instruction to be executed;  
 iv) a program counter base register storing the address of a new method to be invoked;  
 v) a local variable base address to store base address information for local variables in a Java method;  
 vi) a constant pool address to store the base address information for the constant pool in a Java class;  
 vii) a Java stack pointer to track where the top of the JAVA operand stack is; and  
 viii) a RISC stack pointer to point where the RISC can temporarily store variables if the register file is full.  
   
     
     
         14 . The microprocessor of  claim 13  wherein the register file includes a pair of status bits that inform the RISC module to use a value of the top of the JAVA operand stack as a register operand when executing a Java instruction, each of the pair of status bits controlling a source or a destination operand.  
     
     
         15 . The microprocessor of  claim 14  wherein when the status bits are set, the RISC module disregards the source or destination operand and uses the contents of a predefined register as the source or destination operand.  
     
     
         16 . The microprocessor of  claim 14  wherein the status bits are set and cleared by a RISC program that replaces the Java instruction.  
     
     
         17 . The microprocessor of  claim 13  further comprising means for trapping a stack overflow flag when an overflow occurs.  
     
     
         18 . The microprocessor of  claim 17  wherein the means for trapping the stack overflow flag includes means for storing a return address on the top of the RISC stack, means for jumping to a predefined address, means for reading a new branch address and means for switching to a RISC mode and means for branching to the start of a RISC routine.  
     
     
         19 . A method of executing Java code in a RISC processor, said method comprising: 
 executing a first set of Java instructions in the processor with a Java module,    executing a second set of Java instructions in the RISC processor with a RISC module, the second set being more complex than the first set;    interrupting the processor when an instruction too complex for execution by the Java module appears;    executing the complex instruction separately from other instructions in the RISC module; and    returning to the Java module when the RISC module has finished executing the complex instruction.    
     
     
         20 . The method of  claim 19  wherein the interrupting the processor includes: 
 confirming that a set of implementation specific conditions require the processor to be interrupted;  
 storing a return address on the top of a stack in the RISC module;  
 jumping to a predefined address and reading a new branch address;  
 executing a branch instruction to the new branch address in the RISC module; and  
 executing a return instruction to return to program execution using the Java module.