Scalable high performance 3d graphics

Abstract

A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

What is claimed is:  
     
         1 . A method of rendering graphics, comprising: 
 receiving information required to render a graphics scene; and    sending, responsive to the received graphics command, information necessary to render a portion of the graphics scene to one of a plurality of Graphics chips arranged in a loop.    
     
     
         2 . The method of  claim 1 , wherein the receiving is performed by an Interface chip in the loop.  
     
     
         3 . The method of  claim 1 , wherein the sending is performed by an Interface chip in the loop.  
     
     
         4 . The method of  claim 1 , wherein the sending includes distributing graphics primitive commands to respective multiple ones of the Graphics chips in the loop.  
     
     
         5 . The method of  claim 1 , wherein the sending includes sending graphics state information.  
     
     
         6 . The method of  claim 1 , wherein each Graphics chip contains an interleaved portion of a frame buffer.  
     
     
         7 . The method of  claim 1 , wherein the sending further comprises an Interface chip using a load balancing method to decide which subset of the plurality of Graphics chips receives the information necessary to render a portion of the graphics scene.  
     
     
         8 . The method of  claim 1 , where, one of the plurality of Graphics chips receives the portion of information required to render the graphics scene and passes it on to a next Graphics chip in the loop if the receiving Graphics chip is not a final destination.  
     
     
         9 . A method, performed by a Graphics chip in a loop, comprising: 
 receiving information necessary to render a portion of the graphics scene;    performing a portion of a render process for the received information; and    sending a result of the performing step to at least one of a plurality of other Graphics chips in the loop to continue the rendering process.    
     
     
         10 . The method of  claim 9 , wherein sending includes sending graphics primitive commands from the Interface chip to the Graphics chips.  
     
     
         11 . The method of  claim 9 , wherein sending includes state information from the Interface chip to the Graphics chips.  
     
     
         12 . The method of  claim 9 , where the received information contains information to render a primitive object.  
     
     
         13 . The method of  claim 9 , where the Interface chip assigns a subset of the plurality of Graphics chips in the loop to render the portion of the graphics scene.  
     
     
         14 . The method of  claim 9 , wherein the portion of the render process includes a clip checking operation.  
     
     
         15 . The method of  claim 9 , wherein the portion of the render process includes a clipping operation if needed.  
     
     
         16 . The method of  claim 9 , wherein the portion of the render process includes vertex shading.  
     
     
         17 . The method of  claim 9 , wherein the portion of the render process includes scan converting.  
     
     
         18 . The method of  claim 9 , wherein the portion of the render process includes subjecting each generated pixel to a programmable pixel shader.  
     
     
         19 . The method of  claim 9 , wherein the portion of the render process includes subjecting each generated micropolygon vertex to a programmable shader.  
     
     
         20 . The method of  claim 9 , wherein the portion of the render process includes texture operations.  
     
     
         21 . The method of  claim 9 , wherein the portion of the render process includes displacement mapping.  
     
     
         22 . The method of  claim 9 , wherein the portion of the render process includes tessellation of higher order surfaces.  
     
     
         23 . The method of  claim 9  where sending a result of the performing step includes multicasting the screen space boundaries of the projected graphics primitive to all the Graphics chips, along with the plane equation of Z.  
     
     
         24 . The method of  claim 9 , wherein each Graphics chip contains an interleaved portion of a frame buffer.  
     
     
         25 . The method of  claim 24 , where the continuation of the render process performed by one of the Graphics chips renders into an interleaved portion of the frame buffer owned by that Graphics chip.  
     
     
         26 . The method of  claim 25 , where rendering into the interleaved portion of the frame buffer includes performing a sample fill operation.  
     
     
         27 . The method of  claim 24 , further comprising: 
 generation of a video output signal by incrementally gathering information from the interleaved frame buffers of the Graphics chips.    
     
     
         28 . The method of  claim 27 , wherein the gathered information is subject to antialiasing processing.  
     
     
         29 . The method of  claim 27 , wherein antialiasing processing is incrementally performed on each Graphics chip.  
     
     
         30 . The method of  claim 27 , wherein an Interface chip in the loop initiates generation of the information gathering from the Graphics chips.  
     
     
         31 . The method of  claim 9 , wherein each Graphics chip has a copy of texture information.  
     
     
         32 . The method of  claim 31 , wherein the texture information includes a texture map.  
     
     
         33 . The method of  claim 27 , further including, after the rendering process, sending a rendered image to the Graphics chips for use as a texture.  
     
     
         34 . A graphics method, performed by a Graphics chip in a loop, comprising: 
 receiving, by a current Graphics chip from an Interface chip in the loop, a graphics primitive command to render a graphics primitive, and passing the graphics primitive command to a next Graphics chip in the loop if the graphics primitive command is not intended for the current Graphics chip,    performing, by the current Graphics chip, a portion of a rendering process on if the graphics primitive command is intended for the current Graphics chip;    sending a result of the performing step to at least one of a plurality of other Graphics chips to continue the rendering process; and    generation, of a video output signal, at the initiaion of the Interface chip, by incrementally gathering information from interleaved frame buffers of the Graphics chips.    
     
     
         35 . The apparatus of  claim 34 , wherein the performing step obtains texture data from a memory associated with the Graphics chip.  
     
     
         36 . A loop architecture formed of only two types of chips, including: 
 a plurality of Graphics chips in a loop, each Graphics chip having an interleaved portion of a frame buffer; and    at least one LoopInterface chip in the loop to handle external communication for the loop and for communicating with the Graphics chips.    
     
     
         37 . The architecture of  claim 36 , wherein each one of the plurality of Graphics chips has an associated memory containing texture information.  
     
     
         38 . The architecture of  claim 36 , wherein each one of the plurality of Graphics chips has an associated memory containing an interleaved portion of the frame buffer.  
     
     
         39 . The architecture of  claim 36 , where the loop has a single ring schematic.  
     
     
         40 . The architecture of  claim 36 , where the loop has a double ring schematic  
     
     
         41 . The architecture of  claim 36  further including at least one shortcut connection.  
     
     
         42 . The method of  claim 9 , wherein the portion of the render process includes processing the graphics primitive by a transforming operation.