Structure and method for fine pitch flip chip substrate

Abstract

The present invention relates to a Fine Pitch flip chip substrate. A black oxide dam is made on the metal circuit between bump pads to replace the conventional solder resist so that the bump pads will not be buried in the solder resist. A small vias is drilled by laser drilling and plated filled with copper to be used as the connection between the circuits. By this way, the density and the flexibility of routing could be improved. A mesh pattern can be made in the limited space to increase the stiffness of the substrate.

What is claimed is:  
     
         1 . A method for making a fine pitch flip chip substrate, comprising the steps of: 
 providing a substrate, with a first metal layer, the said substrate having a plurality of through holes, a first metal plated layer on the first metal layer and the through holes;    forming an inner circuit on said substrate;    forming a black oxide inner circuit by oxidizing said inner circuit;    forming a dielectric layer and a second metal layer on said substrate;    forming vias in the dielectric layer by drilling to form a plurality of dielectric layer vias, and a second metal plated layer formed in said vias, which are plated and filled to form the surface of the second metal plated layer;    forming a circuit layer on said second metal layer;    forming a plurality of solder resist opening areas on said second metal layer excluding IC bump pad area;    forming a plurality of black oxide dams on said second metal layer by oxidization;    packaging flip chip by under g said IC bumping area, connecting the through holes of the flip chip substrate and said vias of the dielectric layer.    
     
     
         2 . The method as claimed in  claim 1 , wherein in the step of providing a substrate which is made of Bismaleimide Triazine (BT), other organic material, or even ceramics. The thickness of substrate is about 0.1 to 0.4 mm.  
     
     
         3 . The method as claimed in  claim 1 , wherein in the step of providing a substrate, the first metal layer is made of Copper (Cu) with a thickness of 12 μm.  
     
     
         4 . The method as claimed in  claim 1 , wherein in the step of providing a substrate, a plurality of through holes on the substrate is drilled by mechanical or laser drilling. Each of the through holes  203  has a diameter of 100 to 250 μm.  
     
     
         5 . The method as claimed in  claim 1 , wherein in the step of providing a substrate, a first metal plated layer forming on the first metal layer and the through holes is made of Copper (Cu) with a thickness of 15 μm.  
     
     
         6 . The method as claimed in  claim 1 , wherein in the step of forming a dielectric layer and a second metal layer, the dielectric layer is made of Bismaleimde Triazing (BT or other dielectric material.  
     
     
         7 . The method as claimed in  claim 1 , wherein in the step of forming a dielectric layer and a second metal layer, the metal foil is made of Copper (Cu) with a thickness of 12 μm.  
     
     
         8 . The method as claimed in  claim 7 , wherein in the step of forming a dielectric layer and a second metal layer, the foil is laminated to form the second metal layer with a thickness of 7 to 9 μm.  
     
     
         9 . The method as claimed in  claim 1 , wherein in the step of forming vias in the dielectric layer by laser beams, a plurality of dielectric layer vias with a diameter of 100 μm are drilled by laser drilling and the second metal plated layer is laminated to a thickness of 7 to 9 μm.  
     
     
         10 . The method as claimed in  claim 1 , wherein in the step of forming a circuit layer, the Ni/Au layer is formed by way of electro-plating and has a thickness of 5 μm. The Ni/Au layer is used as the connection area of flip chip bumps.  
     
     
         11 . The method as claimed in  claim 1 , wherein in the step of forming a circuit layer, a, liquid photo resist agent or dry film pressing process is used as a mask.  
     
     
         12 . The method as claimed in  claim 1 , wherein in the step of forming a circuit layer, a mesh pattern is designed in the circuit layer to reinforce the stiffness of the substrate and reduce the heat deformation that could cause substrate warpage or twist.  
     
     
         13 . The method as claimed in  claim 1 , wherein in the step of forming a plurality of solder resist areas, the solder resist is a photo solder resist coated with Epoxy.  
     
     
         14 . The method as claimed in  claim 1 , wherein in the step of forming a plurality of black oxide dams, the thickness of the black oxide dams is below 1-3 μm.  
     
     
         15 . A fine pitch flip chip substrate comprising: 
 a fist metal layer formed on the substrate, a plurality of through holes defined through the substrate, a first metal plated layer being made on the first metal layer and the through holes;    an inner layer circuit, etching the first metal layer and the fiat metal plated layer according to the mask to form a plurality of traces, the remained metal portion becoming the inner layer circuit;    black oxide inner layer circuit formed at the surface of the metal circuit of the inner layer circuit;    a dielectric layer being formed by laminating dielectric material on the though holes of the substrate and cover the entire inner layer circuit, a metal foil formed on the dielectric layer and laminated to be the second metal layer;    vias in the dielectric layer and a second metal plated layer formed in the dielectric layer vias which are plated and filled by copper;    a circuit layer formed by plating Ni/Au layer on the second metal layer;    a plurality of solder resist opening areas formed on the second metal layer excluding IC bump pad area;    a plurality of black oxide dams being formed dams on the surface of the IC bump pad connected trace.    
     
     
         16 . The substrate claimed as in  claim 15 , wherein the substrate which is made of Bismaleimide Triazine (BT), other organic material, or even ceramics. The thickness of substrate is about 0.1 to 0.4 mm.  
     
     
         17 . The substrate claimed as in  claim 15 , wherein the first metal layer is made of Copper (Cu) with a thickness of 12 μm.  
     
     
         18 . The substrate claimed as in  claim 15 , wherein a plurality of through holes on the substrate are drilled by mechanical or laser drilling. Each of the through holes  203  has a diameter of 100 to 250 μm.  
     
     
         19 . The substrate claimed as in  claim 15 , wherein a first metal plated layer forming on the first metal layer and the through holes is made of Copper (Cu) with a thickness of 15 μm.  
     
     
         20 . The substrate claimed as in  claim 15 , wherein the dielectric layer is made of Bismaleimide Triazing (BT) or other dielectric material.  
     
     
         21 . The substrate claimed as in  claim 15 , wherein a plurality of dielectric layer vias with a diameter of 100 μm are drilled by laser drilling and the metal foil may be made of Copper (Cu) with a thickness of 12 μm.  
     
     
         22 . The substrate as claimed in  claim 21 , wherein the foil is laminated to form the second metal layer with a thickness of 7 to 9 μm.  
     
     
         23 . The substrate as claimed in  claim 21 , wherein the Ni/Au layer is formed by way of electroplating and has a thickness of 5 μm. The Ni/Au layer is used as the connection area of flip chip bumps.  
     
     
         24 . The substrate as claimed in  claim 21 , wherein a liquid photo resist agent or dry film pressing process is used as a mask.  
     
     
         25 . The substrate as claimed in  claim 21 , wherein a mesh pattern is designed in the circuit layer to reinforce the stiffness of the substrate and reduce the heat deformation that cause substrate warpage or twist.  
     
     
         26 . The substrate as claimed in  claim 21 , wherein the solder resist is a photo solder resist coated with Epoxy.  
     
     
         27 . The substrate as claimed in  claim 21 , wherein the thickness of the black oxide dams is below 1-3 μm.