Semiconductor device

Abstract

A semiconductor device includes a gate electrode GE electrically connected to a gate portion which is made of a polysilicon film provided in the inside of a plurality of grooves formed in a striped form along the direction of T of a chip region CA wherein the gate electrode GE is formed as a film at the same layer level as a source electrode SE electrically connected to a source region formed between adjacent stripe-shaped grooves and the gate electrode GE is constituted of a gate electrode portion G 1 formed along a periphery of the chip region CA and a gate finger portion G 2 arranged so that the chip region CA is divided into halves along the direction of X. The source electrode SE is constituted of an upper portion and a lower portion, both relative to the gate finger portion G 2, and the gate electrode GE and the source electrode SE are connected to a lead frame via a bump electrode.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 (a) a MISFET formed in a chip region of a semiconductor substrate and having a gate portion, a source portion and a drain portion, each comprised of a first conductor;    (b) a gate electrode which is electrically connected with said gate portion and is comprised of a second conductor having a resistivity lower than said first conductor, said gate electrode including 
 (b1) a first portion formed along a periphery of said chip region and  
 (b2) a second portion connected with said first portion and formed on the inside of said first portion in said chip region;  
   (c) a source electrode which is electrically connected with said source portion and is comprised of said second conductor and which is formed plurally within said chip region; and    (d) a bump electrode formed on the upper portions of said gate electrode and said plural source electrodes, respectively,    (e) wherein said gate electrode and said plural source electrodes are arranged at the same layer level and    (f) wherein said second portion of said gate electrode is arranged between adjacent source electrodes of said plural source electrodes.    
     
     
         2 . The semiconductor device according to  claim 1 , 
 wherein said gate portion and said source portion are, respectively, formed at a first surface of said semiconductor substrate, and    wherein said drain portion is formed at a second surface opposite to said first surface.    
     
     
         3 . The semiconductor device according to  claim 1 , 
 wherein said first conductor is made mainly of silicon and said second conductor is made mainly of aluminium.    
     
     
         4 . The semiconductor device according to  claim 1 , 
 wherein said gate portion is comprised of said first conductor formed within a groove of said semiconductor substrate.    
     
     
         5 . The semiconductor device according to  claim 1 , wherein said gate portion is formed plurally in number in a striped form within said chip region.  
     
     
         6 . The semiconductor device according to  claim 1 , 
 wherein said chip region is substantially in a rectangular form, and    wherein said second portion of said gate electrode extends along the long side of said chip region.    
     
     
         7 . The semiconductor device according to  claim 1 , 
 wherein said gate portion is formed plurally in number within said chip region and    wherein said second portion of said gate electrode extends in a direction intersecting perpendicularly to the extending direction of said gate portion.    
     
     
         8 . The semiconductor device according to  claim 1 , wherein said plural source electrodes contains two source electrodes.  
     
     
         9 . The semiconductor device according to  claim 1 , further comprising: 
 (g) a protective film having openings over said gate electrode and said plural source electrodes, respectively, and    (h) said bump electrodes being, respectively, formed at said openings over said gate electrode and said plural source electrodes and are electrically connected with said gate electrode and said plural source electrodes.    
     
     
         10 . The semiconductor device according to  claim 9 , 
 wherein said semiconductor substrate has a first region and a second region surrounding said first region therewith, and    wherein said MISFET is formed at said first region,    said semiconductor device further comprising: 
 (i) other openings in said protective film  
 wherein said other openings are formed over said first region and also over said plural source electrodes, respectively.  
   
     
     
         11 . The semiconductor device according to  claim 9 , 
 wherein said semiconductor substrate has a first region and a second region surrounding said first region therewith and    wherein said MISFET is formed within said first region, and 
 (i) wherein said plural source electrodes are, respectively, connected with a connection unit formed at the same layer level as the source electrodes,  
   said semiconductor device further comprising: 
 (j) another opening in said protective layer, the opening being formed over said first region and also over a single source electrode among said plural source electrodes.  
   
     
     
         12 . The semiconductor device according to  claim 1 , further comprising: 
 (g) a packaging plate having a plurality of external terminals; and    (h) said plural external terminals being connected with said gate electrode and said plural source electrodes via said bump electrodes, respectively.    
     
     
         13 . A semiconductor device comprising: 
 (a) a MISFET formed in a substantially rectangle-shaped chip region of a semiconductor substrate and having 
 (a1) a gate portion which is formed inside a plurality of grooves arranged in said semiconductor substrate and in a striped form along a short side of said substantially rectangle-shaped chip region and is comprised of a silicon film,  
 (a2) a source portion formed between adjacent grooves of said plural striped grooves and comprised of a first semiconductor region, and  
 (a3) a drain portion formed on a back side of said semiconductor substrate and comprised of a second semiconductor region;  
   (b) a gate electrode which is electrically connected with said gate portion and is comprised of an aluminium film, said gate electrode including: 
 (b1) a first portion formed along a periphery of said chip region;  
 (b2) a second portion connected with said first portion and extending along a long side of said first portion so that said first portion is divided approximately into halves along the long side thereof;  
   (c) two source electrodes which are electrically connected with said source portions, are comprised of said aluminium film, are arranged at the same layer level as said gate electrode and are formed on said chip region divided approximately into halves, respectively; and    (d) a bump electrode formed over said gate electrode and said two source electrodes, respectively.    
     
     
         14 . The semiconductor device according to  claim 13 , further comprising: 
 (e) a protective film having openings over said gate electrode and said two source electrodes; and    (f) said bump electrode being formed in said openings over said gate electrode and said two source electrodes and electrically connected with said gate and said two source electrodes, respectively.    
     
     
         15 . The semiconductor device according to  claim 14 , 
 wherein said semiconductor substrate has a first region and a second region surrounding said first region therewith, and    wherein said MISFET is formed within said first region, said semiconductor device further comprising: 
 (g) other openings in said protective film  
 wherein said other openings are over said first region and also over said two source electrodes, respectively.  
   
     
     
         16 . The semiconductor device according to  claim 14 , 
 wherein said semiconductor substrate has a first region and a second region surrounding said first region therewith, and    wherein said MISFET is formed within said first region, 
 (g) wherein said two source electrodes are connected with each other through said aluminium film in the vicinity of an end portion of the second portion of said gate electrode,  
   said semiconductor device further comprising: 
 (h) other openings in said protective film  
 wherein said other openings are over said first region and also over only either of said two source electrodes.  
   
     
     
         17 . The semiconductor device according to  claim 13 , further comprising: 
 (e) a packaging plate having a plurality of external terminals; and    (f) said plural external terminals being connected with said gate electrode and said two source electrodes through said bump electrodes, respectively.    
     
     
         18 . A semiconductor device comprising: 
 (a) A MISFET having a gate portion which is comprised of a first conductor inside a groove formed in a first surface of a semiconductor substrate, a source portion formed at said first surface, and a drain portion formed at a second surface opposite to said first surface;    (b) a gate electrode and a source electrode which are electrically connected to said gate portion and said source portion, respectively, and both of which serve as a first wiring layer;    (c) bump electrodes formed over said gate portion and said source portion for electric connection with said gate portion and said source portion, respectively.    (d) a second conductor film formed between said gate electrode and one of said bump electrodes for connection therewith and serving as a second wiring layer, and    a third conductor film formed between said source electrode and the other bump electrode for electric connection therewith and serving as said second wiring layer.    
     
     
         19 . The semiconductor device according to  claim 18 , further comprising: 
 (e) a protective film having openings over aid gate electrode and said source electrode, respectively; and    (f) said bump electrodes being formed at said openings over said gate electrode and said source electrode for electric connection with said gate electrode and said source electrode.    
     
     
         20 . A semiconductor device comprising: 
 (a) a MISFET having a gate portion comprised of a first conductor at the inside of a groove formed in a first surface of a semiconductor substrate, a source portion formed at said first surface and a drain portion formed at a second surface opposite to said first surface;    (b) a gate electrode and a source electrode electrically connected to said gate portion and said source portion, respectively, and being positioned at the same layer level;    (c) a protective film having first openings formed over said gate electrode and said source electrode;    (d) a bump electrode formed at the first openings over said gate electrode and said source electrode and electrically connected to said gate electrode and said source electrode; and    (e) a second opening formed in said protective film over said source electrode and serving for inspection.    
     
     
         21 . The semiconductor device according to  claim 20 , 
 wherein said first openings have substantially a circular form in plane.    
     
     
         22 . The semiconductor device according to  claim 20 , wherein said second opening has substantially a rectangular form in plane.  
     
     
         23 . The semiconductor device according to  claim 20 , 
 wherein said MISFET is formed in the chip region of said semiconductor substrate,    wherein said groove is formed as a stripe extending along the first direction,    wherein said gate electrode has a first portion formed along a periphery of said chip region and a second portion extending in such a way that said chip region is divided into a plurality of regions in a second direction intersecting perpendicularly to said first direction, and    wherein the bump electrode electrically connected with said source electrode is formed in said plural divided regions, respectively.