Non-volatile semiconductor memory device

Abstract

A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.

What is claimed is:  
     
         1 . A non-volatile semiconductor memory device comprising: 
 a selection transistor constituted of an MOS transistor having a gate electrode;    a source line connected to one end of the selection transistor;    a word line connected to the gate electrode of the selection transistor;    a cell transistor having a gate electrode which is not electrically connected anywhere so as to be in a floating potential state, one end of the cell transistor being connected to the other end of the selection transistor, the cell transistor being constituted of an MOS transistor having the same polarity as the selection transistor; and    a bit line connected to the other end of the cell transistor.    
     
     
         2 . The non-volatile semiconductor memory device according to  claim 1 , wherein each of the selection transistor and the cell transistor is an N-channel MOS transistor.  
     
     
         3 . The non-volatile semiconductor memory device of  claim 1 , wherein the gate electrodes of the selection transistor and the cell transistor are made of the same conductive layer.  
     
     
         4 . The non-volatile semiconductor memory device according to  claim 1 , wherein a diffusion region having the same conductivity type as a source/drain region of the cell transistor is formed at one portion of a substrate region under the gate electrode on the side of the other end of the cell transistor.  
     
     
         5 . The non-volatile semiconductor memory device according to  claim 1 , wherein when programming is performed in the cell transistor, the source line is supplied with a first voltage, the word line is supplied with a second voltage, and the bit line is supplied with a third voltage.  
     
     
         6 . The non-volatile semiconductor memory device according to  claim 5 , wherein the first voltage is a ground voltage, the second voltage is a voltage of positive polarity, and the third voltage is a voltage of positive polarity different from the second voltage.  
     
     
         7 . The non-volatile semiconductor memory device according to  claim 1 , wherein in erasing data stored in the cell transistor, the source line is provided with the first voltage, the word line is supplied with the second voltage, and the bit line is supplied with the third voltage.  
     
     
         8 . The non-volatile semiconductor memory device according to  claim 7 , wherein each of the first and second voltages is a voltage of positive polarity, and the third voltage is a ground voltage.  
     
     
         9 . The non-volatile semiconductor memory device according to  claim 7 , wherein each of the first, second and third voltages is a voltage of positive polarity and the third voltage is lower than the first and second voltages.  
     
     
         10 . The non-volatile semiconductor memory device according to  claim 1 , wherein when data is read from the cell transistor, the source line is supplied with the first voltage, the word line is supplied with the second voltage, the bit line is supplied with the third voltage.  
     
     
         11 . The non-volatile semiconductor memory device according to  claim 10 , wherein the first voltage is a ground voltage, the second voltage is a voltage of positive polarity, and the third voltage is a voltage of positive polarity which is higher than the first voltage and lower than the second voltage.  
     
     
         12 . A non-volatile semiconductor memory device comprising: 
 a selection transistor constituted of an MOS transistor having a gate electrode;    a source line connected to one end of the selection transistor;    a word line connected to the gate electrode of the selection transistor;    a cell transistor having a gate electrode which is not electrically connected anywhere so as to be in a floating potential state, one end of the cell transistor being connected to the other end of the selection transistor, the cell transistor being constituted of an MOS transistor having the same polarity as the selection transistor; and    a source line connected to the other end of the cell transistor.    
     
     
         13 . The non-volatile semiconductor memory device according to  claim 12 , wherein each of the selection transistor and the cell transistor is an N-channel MOS transistor.  
     
     
         14 . The non-volatile semiconductor memory device of  claim 12 , wherein the gate electrodes of the selection transistor and the cell transistor are made of the same conductive layer.  
     
     
         15 . The non-volatile semiconductor memory device according to  claim 12 , wherein a diffusion region having the same conductivity type as a source/drain region of the cell transistor is formed at one portion of a substrate region under the gate electrode on the side of the other end of the cell transistor.  
     
     
         16 . The non-volatile semiconductor memory device according to  claim 12 , wherein when programming is performed in the cell transistor, the source line is supplied with a first voltage, the word line is supplied with a second voltage, and the bit line is supplied with a third voltage.  
     
     
         17 . The non-volatile semiconductor memory device according to  claim 16 , wherein the first voltage is a ground voltage, the second voltage is a voltage of positive polarity, and the third voltage is a voltage of positive polarity different from the second voltage.  
     
     
         18 . The non-volatile semiconductor memory device according to  claim 12 , wherein in erasing data stored in the cell transistor, the source line is provided with the first voltage, the word line is supplied with the second voltage, and the bit line is supplied with the third voltage.  
     
     
         19 . The non-volatile semiconductor memory device according to  claim 18 , wherein each of the first and second voltages is a voltage of positive polarity, and the third voltage is a ground voltage.  
     
     
         20 . The non-volatile semiconductor memory device according to  claim 18 , wherein each of the first, second and third voltages is a voltage of positive polarity and the third voltage is lower than the first and second voltages.  
     
     
         21 . The non-volatile semiconductor memory device according to  claim 12 , wherein when data is read from the cell transistor, the source line is supplied with the first voltage, the word line is supplied with the second voltage, the bit line is supplied with the third voltage.  
     
     
         22 . The non-volatile semiconductor memory device according to  claim 21 , wherein the first voltage is a ground voltage, the second voltage is a voltage of positive polarity, and the third voltage is a voltage of positive polarity which is higher than the first voltage and lower than the second voltage.