US2004007733A1PendingUtilityA1

Floating gate memory cell and forming method

37
Assignee: MACRONIX INT CO LTDPriority: Jun 26, 2002Filed: Jun 26, 2002Published: Jan 15, 2004
Est. expiryJun 26, 2022(expired)· nominal 20-yr term from priority
Inventors:Tuung Luoh
H10D 64/035H10D 30/6891
37
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Claims

Abstract

A floating gate memory cell comprises a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer. The deposition environment is chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A floating gate memory cell of a type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer, an improvement comprising: 
 at least the portion of the floating gate opposite the first insulation layer being a microcrystalline polysilicon material having a grain size of between about 50-500 Å.    
     
     
         2 . The floating gate memory cell according to  claim 1  wherein the entire floating gate is a microcrystalline polysilicon material having a grain size of between about 50-500 Å.  
     
     
         3 . The floating gate memory cell according to  claim 1  wherein the grain size is between about 50-300 Å.  
     
     
         4 . The floating gate memory cell according to  claim 1  wherein the grain size is between about 200-500 Å.  
     
     
         5 . The floating gate memory cell according to  claim 1  wherein the microcrystalline polysilicon material is an undoped material.  
     
     
         6 . The floating gate memory cell according to  claim 1  wherein the microcrystalline polysilicon material is an in-situ doped-process doped material.  
     
     
         7 . The floating gate memory cell according to  claim 1  wherein the microcrystalline polysilicon material is an undoped process with implant.  
     
     
         8 . A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, comprising: 
 selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D); and    forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.    
     
     
         9 . The method according to  claim 8  wherein the selecting step is carried out with X comprising at least one of. H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl.  
     
     
         10 . The method according to  claim 8  wherein the selecting step is carried out with Y comprising at least one of. H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4.  
     
     
         11 . The method according to  claim 8  wherein the selecting step is carried out with Z comprising at least one of. D2, H2, D3.  
     
     
         12 . The method according to  claim 8  wherein the selecting step is carried out with the reaction gas/second gas being SiD4/D2.  
     
     
         13 . The method according to  claim 8  wherein the selecting step is carried out with the reaction gas/second gas being Si2D6/D2.  
     
     
         14 . The method according to  claim 8  wherein the selecting step is carried out with the reaction gas/second gas comprising at least one of the following: SiD4/D2, SiD4/H2, SiH4/D2.  
     
     
         15 . The method according to  claim 8  wherein the selecting step is carried out with the reaction gas/second gas comprising at least one of the following: Si2D6/D2, Si2D6/H2, Si2H6/D.  
     
     
         16 . The method according to  claim 8  wherein the forming step comprises: 
 depositing an amorphous silicon material for the floating gate; and then  
 treating the amorphous silicon floating gate material to exhibit a desired microcrystalline polysilicon grain structure.  
 
     
     
         17 . The method according to  claim 16  wherein the treating step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 200-500 Å.  
     
     
         18 . The method according to  claim 16  wherein the treating step is carried out by subjecting the amorphous silicon floating gate material to a temperature above about 600° C.  
     
     
         19 . The method according to  claim 8  wherein the forming step takes place with the polysilicon material being deposited with a desired microcrystalline polysilicon grain structure.  
     
     
         20 . The method according to  claim 8  wherein the selecting and forming steps are carried out during an LPCVD procedure.  
     
     
         21 . The method according to  claim 20  wherein the LPCVD process comprises a chosen one of the following processes: furnace, single wafer.  
     
     
         22 . The method according to  claim 8  wherein the LPCVD process comprises a furnace process carried out at a pressure from about 0.1 milliTorr to about 5 Torr and at a temperature of about 5000° C. to about 7000° C.  
     
     
         23 . The method according to  claim 8  wherein the LPCVD process comprises a single wafer process carried out at a pressure from about 10 Torr to about 500 Torr and at a temperature of about 580° C. to about 800° C.  
     
     
         24 . The method according to  claim 8  wherein the forming step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 50-500 Å.  
     
     
         25 . The method according to  claim 8  wherein the forming step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 50-300 Å.  
     
     
         26 . A floating gate memory cell made according to the method of  claim 8 .  
     
     
         27 . A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, comprising: 
 selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas SiX and, optionally, a second gas Y;    the selecting step being carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl and Y comprising at least one of: D2, H2, D3; and    forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.    
     
     
         28 . The method according to  claim 27  wherein the forming step comprises: 
 depositing an amorphous silicon material for the floating gate; and then  
 treating the amorphous silicon floating gate material to exhibit a desired microcrystalline polysilicon grain structure.  
 
     
     
         29 . The method according to  claim 28  wherein the treating step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 200-500 Å.  
     
     
         30 . The method according to  claim 27  wherein the forming step takes place with the polysilicon material being deposited with a grain size of about 50-300 Å.  
     
     
         31 . The method according to  claim 27  wherein at least one of X and Y comprises deuterium (D).  
     
     
         32 . A floating gate memory cell made according to the method of  claim 27 .  
     
     
         33 . A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, comprising: 
 selecting a reaction gas and, optionally, a second gas for forming the floating gate during the deposition process consisting essentially of a reaction gas Si2X and, optionally, a second gas Y;    the selecting step being carried out with X comprising at least one of: H6, H4Cl2, 2Cl4, D6, D4Cl2, D2Cl4 and Y comprising at least one of: D2, H2, D3; and forming a microcrystalline polysilicon floating gate using said selected reaction gas/second gas.    
     
     
         34 . The method according to  claim 33  wherein the forming step comprises: 
 depositing an amorphous silicon material for the floating gate; and then  
 treating the amorphous silicon floating gate material to exhibit a desired microcrystalline polysilicon grain structure.  
 
     
     
         35 . The method according to  claim 34  wherein the treating step is carried out so that the microcrystalline polysilicon floating gate has a grain size of about 200-500 Å.  
     
     
         36 . The method according to  claim 33  wherein the forming step takes place with the polysilicon material being deposited with a grain size of about 50-300 Å.  
     
     
         37 . The method according to  claim 33  wherein at least one of X and Y comprises deuterium (D).  
     
     
         38 . A floating gate memory cell made according to the method of  33 .  
     
     
         39 . A method for forming a polysilicon floating gate during the manufacture of a floating gate memory cell using a deposition process, the floating gate memory cell of a type comprising a substrate with a drain and a source separated by a channel, a floating gate separated from the channel by a first insulation layer, and a control gate separated from the floating gate by a second insulation layer, comprising: 
 choosing a deposition environment comprising: 
 selecting a reaction gas;  
 selecting a reaction gas flow rate;  
 selecting a deposition pressure; and  
 selecting a deposition time;  
   forming a microcrystalline polysilicon floating gate; and    said the selecting steps chosen so that the grain size of at least a portion of the floating gate opposite the first insulation layer is about 50-500 Å.    
     
     
         40 . The method according to  claim 39  wherein the selecting steps are carried out so that the grain size is between about 50-300 Å.  
     
     
         41 . The method according to  claim 39  wherein the reaction gas selecting step comprises: 
 selecting a reaction gas and, optionally, a second gas consisting essentially of a reaction gas SiX or Si2Y or an appropriate combination thereof, and, optionally, a second gas Z, where at least one of X, Y and Z comprises deuterium (D).  
 
     
     
         42 . The method according to  claim 41  wherein the reaction gas selecting step is carried out with X comprising at least one of: H4, H2Cl2, HCl3, D4, D2Cl2, D3Cl.  
     
     
         43 . The method according to  claim 41  wherein the reaction gas selecting step is carried out with Y comprising at least one of: H6, H4Cl2, H2Cl4, D6, D4Cl2, D2Cl4.  
     
     
         44 . The method according to  claim 41  wherein the reaction gas selecting step is carried out with Z comprising at least one of: D2, H2, D3.

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