Insulated-gate field-effect thin film transistors

Abstract

A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor Gated-FET device comprises a lightly doped resistive channel region formed on a first semiconductor thin film layer; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.

What is claimed is:  
     
         1 . A semiconductor Gated-FET device, comprising: 
 a lightly doped resistive channel region formed on a first semiconductor thin film layer; and    an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.    
     
     
         2 . The device in claim- 1  further comprising of said channel region formed between a source region and a drain region in the said first semiconductor thin film; 
 wherein said source region coupled to a source voltage, and said drain region coupled to a drain voltage, and said source and drain regions having a higher level of the same dopant type as said channel region.  
 
     
     
         3 . The device of claim- 1 , wherein the channel comprises one of a single crystal, polycrystalline Silicon, a re-crystallized Silicon, and a semiconductor material.  
     
     
         4 . The device of claim- 1 , wherein the gate comprises one of a conductor, a refractory metal, a heavily doped poly-Silicon and a doped semiconductor material.  
     
     
         5 . The device of claim- 1 , wherein the insulator comprises one of an oxide, an oxynitride, a nitride and a dielectric material.  
     
     
         6 . The device in claim- 2  further comprised of an off state with said gate voltage below a first threshold voltage level; 
 wherein said thin film channel substantially not conducting a current between said drain and source regions for a differential bias voltage ranging from zero to a system power supply voltage.  
 
     
     
         7 . The device in claim- 2  further comprised of an on state with said gate voltage above a first threshold voltage level; 
 wherein said thin film channel substantially conducting a current between said drain and source regions for a differential bias voltage ranging from zero to a system power supply voltage.  
 
     
     
         8 . The device in claim- 2  further comprised of an on state with said gate voltage above a second flat band voltage level; 
 wherein said thin film channel substantially conducting a current between said drain and source regions for a differential bias voltage ranging from zero to a system power supply voltage, and said conducting current substantially enhanced by an accumulation of majority carriers above said channel doping level near the said insulator surface.  
 
     
     
         9 . The device in claim- 2  further comprised of a Gated-NFET device comprising said source, channel and drain regions doped with an N type dopant; 
 wherein said gate material having a positive flat band voltage, and said source region connected to a lower voltage compared to said drain region.  
 
     
     
         10 . The device in claim- 9  further comprises of: 
 an off state defined by said gate to said source voltage difference in a range from a system ground voltage V S  to a first threshold voltage V TN ; and  
 an on state defined by said gate to said source voltage difference in a range from said first threshold voltage V TN  to a system power supply voltage V D .  
 
     
     
         11 . The device in claim- 9  further comprising a P+ doped poly-Silicon gate material; 
 wherein said source and drain regions defined by lightly doped N type tip regions adjacent to said channel region self aligned to said gate edge, and said source and drain regions outside of said lightly doped tip regions fully salicided and self-aligned to said tip regions.  
 
     
     
         12 . The device in claim- 2  further comprised of a Gated-PFET device comprising said source, channel and drain regions doped with a P type dopant; 
 wherein said gate material having a negative flat band voltage, and said source region connected to a higher voltage compared to said drain region.  
 
     
     
         13 . The device in claim- 12  further comprises of: 
 an off state defined by said gate to said source voltage difference in a range from a system ground voltage V S  to a first threshold voltage V TP ; and  
 an on state defined by said gate to said source voltage difference in a range from said first threshold voltage V TP  to a system power supply voltage V D .  
 
     
     
         14 . The device in claim- 12  further comprising an N+ doped poly-Silicon gate material; 
 wherein said source and drain regions defined by lightly doped P type tip regions adjacent to said channel region self aligned to said gate edge, and said source and drain regions outside of said lightly doped tip regions fully salicided and self aligned to said tip regions.  
 
     
     
         15 . The device of claim- 1 , wherein said non-conducting channel resistance is in a range approximately 10 KOhm to 1 TOhm.  
     
     
         16 . The device of claim- 1 , wherein said conducting channel resistance is in a range approximately 100 Ohm to 100 KOhm.  
     
     
         17 . The device of  claim 1 , wherein the ratio of said device conductive channel current to said device non-conductive channel current is in a range approximately 1000 to 10,000,000,000.  
     
     
         18 . The device of claim- 6  and claim- 7  comprised of said first threshold voltage in a range approximately 0.20 to 0.33 times a system power supply voltage.  
     
     
         19 . A method for fabricating a semiconductor Gated-FET device, comprising: 
 depositing a lightly doped resistive channel region formed on a first semiconductor thin film layer; and    depositing an insulator layer above said channel having a gate region formed on a gate material deposited on said insulator layer; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state; and    optimizing said thin film semiconductor channel properties, insulator properties and gate material properties.    
     
     
         20 . The method of  claim 19 , wherein said thin film semiconductor channel properties, insulator properties and gate material properties include: 
 a first thickness by X=ε S *T G /ε G ; and    a second thickness by Y=[(2*ε S *(V FB −V T ))/(q*D)] 0.5 ; and    a third thickness by Z=(X 2 +Y 2 ) 0.5 −X and    said thin film channel height T S  is in a range approximately 0.8*Z to 1.2*Z.    where, ε S  is channel semiconductor permittivity, ε G  is insulator permittivity, T G  is insulator thickness, V FB  is gate to semiconductor absolute flat band voltage, V T  is channel region absolute threshold voltage, q is electron charge, D is channel doping level and T S  is channel semiconductor layer thickness.    
     
     
         21 . The method of claim- 19  further comprising forming a heavily doped poly-Silicon gate material, oxide insulator and lightly doped Silicon channel region having: 
 a first thickness by X=3*T OX  (Å); and  
 a second thickness by Y=0.28/{square root}D (Å); and  
 a third thickness by Z=(X 2 +Y 2 ) 0.5 −X (Å); and  
 said thin film channel height T S  is in a range 0.8*Z to 1.2*Z.  
 where, T OX  is oxide insulator thickness in Å, D is channel doping level in atoms/(Å) 3  and T S  is channel semiconductor layer thickness in Å.  
 
     
     
         22 . The method of claim- 19 , wherein a thin film process sequence is inserted to a logic process at a first contact level comprised of: 
 applying C1 mask and etching contacts;    forming W-silicide plug and performing CMP;    depositing crystalline poly-1 (P1);    performing-P1 mask & etching P1;    applying blanket Gated-NFET V T  N− implant;    applying Gated-PFET V T  mask & P− implant;    depositing Gox;    depositing amorphous poly-2 (P2);    applying blanket P+ implantation of Gated-NFET Gate;    applying N+ mask & implanting Gated-PFET Gate;    applying P2 mask & etching P2;    applying blanket LDN N implant (Gated-NFET LDD);    applying LDP mask & P implant (Gated-PFET LDD);    depositing a spacer oxide and etching the spacer oxide;    depositing Nickel;    salicidizing the Nickel on exposed P1 and P2;    salicidizing P1 completely;    performing RTA anneal—P1 and P2 re-crystallization and dopant anneal;    depositing ILD oxide & CMP;    applying C2 mask & etch;    forming a W plug & CMP; and    depositing M1.    
     
     
         23 . The method of claim- 19 , further comprising a thinned down SOI process sequence including: 
 forming SOI substrate wafer;    performing Shallow Trench isolation: Trench Etch, Trench Fill and CMP;    depositing Sacrificial oxide;    applying Periphery PMOS V T  mask & implant;    applying Periphery NMOS V T  mask & implant;    applying Gated-FET mask and Silicon etch;    performing Gated-FET blanket V T  N implant;    applying Gated-FET V T  P mask and P implant;    performing Dopant activation and anneal;    performing Sacrificial oxide etch;    depositing Gate oxide/Dual gate oxide option;    depositing Gate poly (GP);    applying Gated-FET N+ mask and N+ implant;    applying Gated-FET P+ mask and P+ implant;    applying GP mask & etch;    applying LDN mask & N− implant;    applying LDP mask & P− implant;    depositing Spacer oxide & spacer etch;    applying Periphery N+ mask and N+ implant;    applying Periphery P+ mask and P+ implant;    depositing Ni;    performing RTA anneal—Ni salicidation (S/D/G regions & interconnect);    performing Dopant activation;    performing Unreacted Ni etch;    depositing ILD oxide & CMP; and    applying C mask and etch.    
     
     
         24 . A non planar integrated circuit comprising: 
 a substrate surface used to build a plurality of logic transistors in a first plane; and    an isolation layer deposited above said substrate surface substantially parallel to said first plane; and    a second plane substantially different from said first plane; and    a semiconductor Gated-FET device formed above said isolation layer comprising: 
 a lightly doped resistive channel region formed on a first semiconductor thin film layer wherein said channel region having a surface parallel to said second plane; and  
 an insulator layer deposited on said channel surface wherein said insulator surface is substantially parallel to said second plane; and  
 a gate region formed on a gate material deposited on said insulator layer wherein said gate material surface is substantially parallel to said second plane; said gate region receiving a gate voltage having a first level modulating said channel resistance to a substantially non-conductive state and a second level modulating said channel resistance to a substantially conductive state.