US2004003943A1PendingUtilityA1

Multilayer circuit board and method of manufacturing the same

Assignee: FUJITSU LTDPriority: Aug 31, 2000Filed: Jul 7, 2003Published: Jan 8, 2004
Est. expiryAug 31, 2020(expired)· nominal 20-yr term from priority
Inventors:Kenji Iida
Y10T29/49165H05K 2203/054H05K 3/045Y10T29/49155Y10T29/49156H05K 2203/0733Y10T29/49128H05K 3/243H05K 2203/0542H05K 2201/09881H05K 3/108H05K 3/4647H05K 2203/025
40
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Claims

Abstract

In the multilayer circuit board, cable patterns in a plurality of cable layers can be precisely formed, and the cable layer are formed with higher density, with higher reliability. The multilayer circuit board comprises: a plurality of cable layers, each of which includes electric conductive sections; a plurality of first insulating layers, each of which encloses the electric conductive sections in each cable layer and fills spaces between the electric conductive sections; and post vias electrically connecting the electric conductive sections in one cable layer to those in another cable layer. Height of the electric conductive sections in each cable layer are equal to that of the first insulating layer enclosing those electric conductive sections.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A multilayer circuit board, 
 comprising: 
 a plurality of cable layers, each of which includes electric conductive sections;  
 a plurality of first insulating layers, each of which encloses said electric conductive sections in each cable layer and fills spaces between said electric conductive sections; and  
 post vias electrically connecting said electric conductive sections in one cable layer to those in another cable layer, 
 wherein height of said electric conductive sections in each cable layer are equal to that of said first insulating layer enclosing those electric conductive sections.  
 
   
     
     
         2 . The multilayer circuit board according to  claim 1 , 
 further comprising a second insulating layer, which is formed to enclose said post vias, 
 wherein height of said post vias are equal to that of said second insulating layer.  
   
     
     
         3 . A method of manufacturing a multilayer circuit board, 
 comprising the steps of: 
 forming a plurality of cable layers, each of which includes electric conductive sections;  
 forming a plurality of first insulating layers, each of which encloses said electric conductive sections in each cable layer; and  
 forming post vias, which electrically connect said electric conductive sections in one cable layer to those in another cable layer, 
 wherein said electric conductive sections of each cable layer are formed by the steps of: 
 forming a first electric conductive layer;  
 forming a first resist layer, whose thickness is equal to that of said electric conductive sections to be formed, on a surface of said first electirc conductive layer;  
 etching said first resist layer so as to expose parts of said first electric conductive layer corresponding to said electric conductive sections to be formed; and  
 executing electrolytic plating on the exposed parts of said first electric conductive layer so as to cast up said exposed parts and form said electric conductive sections until height of said electric conductive sections are made higher than that of said first resist layer;  
 forming a first stopper metal layer on said first resist layer and said electric conductive sections, which have been casted up by electrolytic plating; and  
 abrading said electric conductive sections until the height of said electric conductive sections are made equal to that of said first resist layer.  
 
 
   
     
     
         4 . The method according to  claim 3 , 
 wherein said electric conductive sections of each cable layer are further treated by the steps of: 
 removing said first stopper metal layer and said first resist layer;  
 removing the exposed parts of said first electric conductive layer; and  
 forming said first insulating layer so as to enclose said electric conductive sections and fill spaces there between.  
   
     
     
         5 . The method according to  claim 3 , 
 wherein said electric conductive sections of each cable layer are further treated by the steps of: 
 removing said first stopper metal layer and said first resist layer;  
 removing the exposed parts of said first electric conductive layer;  
 forming said first insulating layer so as to cover said electric conductive sections and fill spaces there between;  
 forming a second stopper metal layer on said first insulating layer; and  
 abrading said first insulating layer on said electric conductive sections until the height of said electric conductive sections are made equal to that of said first insulating layer.  
   
     
     
         6 . The method according to  claim 3 , 
 wherein said post vias are formed by the steps of: 
 forming a second electric conductive layer on said electric conductive sections and said first insulating layer;  
 forming a second resist layer on said second electric conductive layer;  
 forming via holes in said second resist layer; and  
 executing electrolytic plating in said via holes so as to form said post vias.  
   
     
     
         7 . The method according to  claim 6 , 
 further comprising the steps of: 
 forming a third stopper metal layer on said second resist layer and said post vias; and  
 abrading said post vias until the height of said post vias are made equal to that of said second resist layer.  
   
     
     
         8 . The method according to  claim 6 , 
 further comprising the steps of: 
 removing said second resist layer;  
 forming a second insulating layer, which covers and encloses said post vias;  
 forming a fourth stopper metal layer on said second insulating layer; and  
 abrading parts of said second insulating layer corresponding to said post vias until the height of said post vias are made equal to that of said second insulating layer.  
   
     
     
         9 . The method according to  claim 3 , 
 wherein said cable layers, said insulating layers and said post vias are formed on both sides of a core board.    
     
     
         10 . The method according to  claim 3 , 
 wherein said resist layer is treated to improve hardness thereof.

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