PCI bridge and data transfer methods

Abstract

A bridge for interconnecting a processor to a peripheral device by way of a PCI bus may have a read buffer. The bridge autonomously requests data from the peripheral device and places received data in the read buffer. The processor reads the data from the receive buffer. The bridge may have a write buffer. The bridge accumulates data in the write buffer until a triggering event occurs. Upon the occurrence of a triggering event the bridge sends the data in the receive buffer to the peripheral device in a burst.

What is claimed is:  
     
         1 . Bridge apparatus for permitting a processor to access data from at least one peripheral device, the apparatus comprising: 
 a PCI bus interface;    a processor interface;    a read buffer accessible to a processor by way of the processor interface; and,    a controller configured to periodically request data from one or more peripheral devices by way of the PCI bus interface and to store the requested data in the read buffer for access by the processor.    
     
     
         2 . The bridge apparatus of  claim 1  wherein the controller is configured to periodically request the data from the one or more peripheral devices at a rate in the range of on the order of once every hundreds of microseconds to once every tens of milliseconds.  
     
     
         3 . The bridge apparatus of  claim 1  wherein the data comprises a block of data on the peripheral device.  
     
     
         4 . A system comprising the bridge apparatus of  claim 1  together with a processor connected to the processor interface and a peripheral device connected to the PCI bus interface by way of a PCI bus.  
     
     
         5 . The system of  claim 4  wherein the data comprises a block of data on the peripheral device.  
     
     
         6 . The system of  claim 5  wherein the peripheral device is configured to send the data in the block of data to the read buffer across the PCI bus in one or more bursts.  
     
     
         7 . The system of  claim 6  wherein the PCI bus is configured to deliver the one or more bursts at a lowest priority.  
     
     
         8 . The bridge apparatus of  claim 1  comprising a write buffer, wherein the controller is configured to: 
 receive by way of the processor interface data addressed to contiguous addresses in a peripheral device connected to the bus;  
 accumulate the received data in the write buffer; and,  
 send the accumulated data in one or more bursts to the peripheral device by way of the PCI bus interface upon the occurrence of one of one or more triggering events, the one or more triggering events including a receipt by way of the processor interface of data addressed to an address non-contiguous with the received data.  
 
     
     
         9 . The bridge apparatus of  claim 8  wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.  
     
     
         10 . The bridge apparatus of  claim 9  wherein the threshold amount of data is 64 long words.  
     
     
         11 . The bridge apparatus of  claim 8  wherein the one or more triggering events include the passage of a specified time since the oldest data was written to the write buffer.  
     
     
         12 . The bridge apparatus of  claim 8  wherein the one or more triggering events include the bridge apparatus determining by way of the processor interface that the processor is attempting to communicate with another device.  
     
     
         13 . The bridge apparatus of  claim 8  wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface for transmission to a peripheral device data consisting of less than one full long word.  
     
     
         14 . The bridge apparatus of  claim 8  wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface a read request.  
     
     
         15 . A system comprising the bridge apparatus of  claim 8  together with a processor connected to the processor interface and a peripheral device connected to the PCI bus interface by way of a PCI bus.  
     
     
         16 . The system of  claim 15  wherein the data comprises a block of data on the peripheral device.  
     
     
         17 . The system of  claim 16  wherein the peripheral device is configured to send the data in the block of data to the read buffer across the PCI bus in one or more bursts.  
     
     
         18 . The system of  claim 17  wherein the PCI bus is configured to deliver the one or more bursts at a lowest priority.  
     
     
         19 . The system of  claim 15  wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.  
     
     
         20 . The system of  claim 19  wherein the threshold amount of data is  64  long words.  
     
     
         21 . The system of  claim 15  wherein the one or more triggering events include the passage of a specified time since the oldest data was written to the write buffer.  
     
     
         22 . The system of  claim 15  wherein the one or more triggering events include the bridge apparatus determining by way of the processor interface that the processor is attempting to communicate with another device.  
     
     
         23 . The system of  claim 15  wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface for transmission to a peripheral device data consisting of less than one full long word.  
     
     
         24 . The system of  claim 15  wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface a read request.  
     
     
         25 . The system of  claim 15  wherein the peripheral device comprises an ATM traffic shaper.  
     
     
         26 . The bridge apparatus of  claim 8  comprising a plurality of write buffers wherein, the controller is configured to accumulate the received data in a first one of the plurality of write buffers and, upon receiving by way of the processor interface, the data addressed to an address non-contiguous with the received data, place the data addressed to an address non-contiguous with the received data into a second one of the plurality of write buffers.  
     
     
         27 . The bridge apparatus of  claim 26  wherein the plurality of write buffers comprises at least four write buffers.  
     
     
         28 . The bridge apparatus of  claim 1  wherein the PCI bus interface, processor interface; read buffer and controller are implemented on a Field Programmable Gate Array.  
     
     
         29 . A computer readable medium containing instructions for configuring a field programmable gate array to implement the bridge apparatus of  claim 28 .  
     
     
         30 . The bridge apparatus of  claim 8  wherein the PCI bus interface, processor interface; read buffer and controller are implemented on a Field Programmable Gate Array.  
     
     
         31 . A computer readable medium containing instructions for configuring a field programmable gate array to implement the bridge apparatus of  claim 30 .  
     
     
         32 . Apparatus for permitting a processor to write data to at least one peripheral device, the apparatus comprising: 
 a PCI bus interface;    a write buffer accessible to the processor;    a controller configured to: 
 receive by way of the processor interface data addressed to contiguous addresses in a peripheral device accessible by way of the PCI bus interface;  
 accumulate the received data in a write buffer; and,  
 upon the occurrence of one or one or more triggering events, send the accumulated data to the contiguous addresses as a burst by way of the PCI bus interface;  
   wherein the one or more triggering events include a receipt by way of the processor interface of data addressed to an address non-contiguous with data accumulated in the write buffer.    
     
     
         33 . The bridge apparatus of  claim 32  wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.  
     
     
         34 . The bridge apparatus of  claim 33  wherein the threshold amount of data is 64 long words.  
     
     
         35 . The bridge apparatus of  claim 32  wherein the one or more triggering events include the passage of a specified time since an oldest data was written to the write buffer.  
     
     
         36 . The bridge apparatus of  claim 32  wherein the one or more triggering events include the bridge apparatus determining by way of the processor interface that the processor is attempting to communicate with another device.  
     
     
         37 . The bridge apparatus of  claim 32  wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface for transmission to a peripheral device data consisting of less than one full long word.  
     
     
         38 . The bridge apparatus of  claim 32  wherein the one or more triggering events include the bridge apparatus receiving by way of the processor interface a read request.  
     
     
         39 . The bridge apparatus of  claim 32  comprising a plurality of write buffers wherein, the controller is configured to: 
 accumulate the received data in a first one of the plurality of write buffers; and  
 upon receiving by way of the processor interface, the data addressed to an address non-contiguous with the received data, place the data addressed to an address non-contiguous with the received data into a second one of the plurality of write buffers.  
 
     
     
         40 . The bridge apparatus of  claim 39  wherein the plurality of write buffers comprises at least four write buffers.  
     
     
         41 . A method for transferring data across a bus, the method comprising: 
 at a bridge connected to the bus, receiving from a processor data addressed to contiguous addresses in a peripheral device connected to the bus and accumulating the received data in a write buffer;    sending the accumulated data to the peripheral device upon the occurrence of one of one or more triggering events, the one or more triggering events including a receipt from the processor of data addressed to a non-contiguous address.    
     
     
         42 . The method of  claim 41  wherein the bus comprises a PCI bus.  
     
     
         43 . The method of  claim 42  wherein the one or more triggering events include the presence in the write buffer of a threshold amount of data.  
     
     
         44 . The method of  claim 41  wherein the threshold amount of data is 64 long words.  
     
     
         45 . The method of  claim 42  wherein the one or more triggering events include the passage of a specified time since an oldest data was written to the write buffer.  
     
     
         46 . The method of  claim 42  wherein the one or more triggering events include the processor attempting to communicate with a device other than the bridge.  
     
     
         47 . The method of  claim 42  wherein the one or more triggering events include the bridge receiving for transmission to a peripheral device data consisting of less than one full long word.  
     
     
         48 . The method of  claim 42  wherein the one or more triggering events include the bridge receiving a read request.  
     
     
         49 . The method of  claim 42  wherein the peripheral device comprises a traffic shaper.  
     
     
         50 . The method of  claim 42  comprising: 
 at the bridge, periodically generating requests for data from at least one peripheral device;  
 in response to the requests for data receiving one or more bursts of data from the at least one peripheral device; and,  
 storing the received data in a read buffer accessible to the processor.  
 
     
     
         51 . The method of  claim 50  wherein the peripheral device comprises a traffic shaper.  
     
     
         52 . The method of  claim 51  comprising generating the requests with a period in the range of on the order of once every one request per 100 microseconds to one request per 100 milliseconds.  
     
     
         53 . The method of  claim 51  comprising generating the requests with a period in the range of one request per 1 millisecond to one request per 10 milliseconds.  
     
     
         54 . The method of  claim 50  comprising sending the one or more bursts of data from the peripheral device to the bridge at a low priority.