Method and system for the transmission, reception and processing of 4-level and 8-level signaling symbols

Abstract

A method and system for the transmission, reception, and processing of 4-level and 8-level signaling symbols is provided. An inventive modulator is provided for modulating 4-level signaling symbols using an 8-level modulator. Further, this inventive modulator is able to produce 4-level modulation when modulating 4-level signaling symbols using an 8-level modulator, where the 4-level modulation represents the 4-level symbol sequence modulated. Further, a constrained/unconstrained demodulator is provided which is able to demodulate both 4-level signaling symbols and 8-level signaling symbols. The inventive demodulator accomplishes this by limiting the number of new symbol hypotheses and path histories to 4 when working with 4-level signaling symbols, and setting the number of new symbol hypotheses and path histories to 8 when working with 8-level signaling symbols. Additionally, an error correction decoder is provided which is also able to decode a demodulated signal which contains both 4-level and 8-level signaling symbols. The inventive error correction decoder accomplishes this by utilizing an interleaver that only places bits in the 2-bit positions of the 3-PSK soft values that correspond to the 2-bits of QPSK to decode 4-level signalling symbols, and utilizing an interleaver that places bits in all three of the possible bit positions of a symbol to decode 8-level signalling symbols.

1 . A method for modulating 4-level signaling symbols using an 8-level modulator, the method comprising: 
 receiving 4-level signaling symbols to be modulated, each 4-level signaling symbol containing 2-bits of information;    expanding said 4-level signaling symbols into 8-level signaling symbols, each 8-level signaling symbol containing 3-bits of information; and    modulating said 8-level signaling symbols.    
     
     
         2 . The method of  claim 1  wherein the step of expanding said 4-level signaling symbols into 8-level signaling symbols includes manufacturing a third bit for each 4-level signaling symbol and appending said third bit to said 2-bits of information.  
     
     
         3 . The method of  claim 2  wherein said third bit is the exclusive-OR of said 2-bits.  
     
     
         4 . The method of  claim 1  further comprising performing a progressive 45° phase shift between a modulation of consecutive symbols.  
     
     
         5 . The method of  claim 1  wherein modulating an expanded 4-level signaling symbol with the 8-level modulator causes the 8-level modulator to produce 4-level modulation.  
     
     
         6 . The method of  claim 1  wherein said 4-level signaling symbols are a subset of said 8-level signaling symbols.  
     
     
         7 . The method of  claim 1  further comprising the step of sending an indication signal indicating which of expanded 4-level signaling symbols and 8-level signaling symbols are being transmitted.  
     
     
         8 . Method for demodulating a received signal containing at least one of 4-level modulation and 8-level modulation, the method comprising: 
 demodulating said received signal under a first assumption that said received signal contains 4-level modulation and determining a value of a first quality factor by performing error correction decoding on symbols demodulated under said first assumption;    demodulating said received signal under a second assumption that said received signal contains 8-level modulation and determining a value of a second quality factor by performing error correction decoding on symbols demodulated under said second assumption;    determining a received modulation present in said received signal using said first and said second quality factors; and    demodulating said received signal as said received demodulation.    
     
     
         9 . The method of  claim 8  wherein the step of determining from said first and said second quality factors may be performed before said demodulation under the first and the second assumptions is completed.  
     
     
         10 . The method of  claim 8  wherein said first and said second quality factors are determined using metrics generated by an error correction decoder.  
     
     
         11 . Method for demodulating a received signal containing at least one of 4-level modulation and 8-level modulation, the method comprising: 
 determining whether 4-level modulation or 8-level modulation is present in said received signal;    if it is determined that 4-level modulation is present in said received signal, operating a demodulator in a constrained 4-level demodulation mode by restricting possible levels for the received signal to four levels, determining which level out of said four levels is being received, and producing 4-level signaling symbol decisions having 2-bits each; and    if it is determined that 8-level modulation is present in said received signal, operating said demodulator in an unconstrained 8-level demodulation mode by determining which level out of eight possible levels is being received, and producing 8-level signaling symbol decisions having 3-bits each.    
     
     
         12 . The method of  claim 11  wherein the step of determining whether 4-level modulation or 8-level modulation is present further comprises the step of receiving an indication signal indicating whether 4-level modulation or 8-level modulation is present in said received signal.  
     
     
         13 . The method of  claim 12  wherein said indication signal is transmitted using at least one of a SYNCWORD, a CDVCC, and a FACCH message.  
     
     
         14 . The method of  claim 11  wherein the step of determining whether 4-level modulation or 8-level modulation is present further comprises the step of using a predetermined transmission format to determine whether a 4-level signaling symbol or an 8-level signaling symbol is present in said received signal.  
     
     
         15 . The method of  claim 11  wherein said 4-level and said 8-level signaling symbol decisions are soft 4-level and 8-level signaling symbol decisions.  
     
     
         16 . The method of  claim 11  wherein the step of operating said demodulator in said constrained 4-level demodulation mode and said unconstrained 8-level demodulation mode further comprises the step of performing a sequential maximum likelihood sequence estimation process.  
     
     
         17 . Method for decoding a received signal containing at least one of 4-level signaling symbols and 8-level signaling symbols, the method comprising: 
 receiving a signal;    demodulating said received signal as 8-level modulation;    determining whether 4-level signaling symbols or 8-level signaling symbols are present in said received signal;    if it is determined that 4-level signaling symbols are present in said received signal, selecting and deinterleaving two bitwise-soft-information values from the 4-level symbols and processing them in an error correction decoder; and    if it is determined that 8-level signals are present in said received signal, selecting and deinterleaving three bitwise-soft-information values from the 8-level symbols and processing them in an error correction decoder.    
     
     
         18 . The method of  claim 17  wherein the step of determining whether 4-level signaling symbols or 8-level signaling symbols are present further comprises the step of receiving an indication signal indicating whether 4-level signaling symbols or 8-level signaling symbols are present in said received signal.  
     
     
         19 . The method of  claim 18  wherein said indication signal is transmitted using at least one of a SYNCWORD, a CDVCC, and a FACCH message.  
     
     
         20 . The method of  claim 17  wherein the step of determining whether 4-level signaling symbols or 8-level signaling symbols are present further comprises the step of using a predetermined transmission format to determine whether 4-level signaling symbols or 8-level signaling symbols are present in said received signal.  
     
     
         21 . The method of  claim 17  wherein the step of processing using an error correction decoder further comprises the step of performing a sequential maximum likelihood sequence estimation process.  
     
     
         22 . The method of  claim 17  wherein the step of processing said soft information from 4-level symbols includes removing a third bit from 8-level symbols.  
     
     
         23 . Method for decoding a received signal containing at least one of 4-level signaling symbols and 8-level signaling symbols, the method comprising: 
 receiving a signal;    demodulating said received signal as 8-level modulation;    performing error correction decoding under a first assumption that a 4-level signaling symbols are present in the received signal and determining a first quality factor;    performing error correction decoding under a second assumption that 8-level signaling symbols are present in the received signal and determining a second quality factor;    determining a received modulation in said received signal using said first and second quality factors; and    decoding said received signal as said received modulation.    
     
     
         24 . The method of  claim 23  wherein the step of determining from said first and said second quality factors may be performed before said decoding under the first and the second assumptions is completed.  
     
     
         25 . The method of  claim 23  wherein said first and second quality factors are determined using metrics created from said error correction decoding under said first and said second assumptions.  
     
     
         26 . A system for modulating 4-level signaling symbols using an 8-level signaling symbol modulator comprising: 
 a processor for processing information into a plurality of 4-level signaling symbols to be modulated;    an expander coupled to said processor for expanding said plurality of 4-level signaling symbols each containing 2-bits of information to expanded 8-level signaling symbols each containing 3-bits of information; and    an 8-level modulator coupled to said expander for modulating said expanded 8-level signaling symbols.    
     
     
         27 . The system of  claim 26  wherein said expander expands said plurality of 4-level signaling symbols by XORing said 2-bits of information to generate a third bit and appends said third bit to said 2-bits of information.  
     
     
         28 . The system of  claim 26  wherein said 8-level modulator applies a progressive 45° phase shift between a modulation of consecutive symbols.  
     
     
         29 . The system of  claim 26  wherein said 4-level signaling symbols are a subset of said expanded 8-level signaling symbols.  
     
     
         30 . The system of  claim 26  wherein said 8-level modulator produces 4-level modulation when modulating said expanded 8-level signaling symbols.  
     
     
         31 . The system of  claim 26  wherein said information processed by said processor indicates a presence of said expanded 8-level signaling symbols.  
     
     
         32 . The system of  claim 26  wherein said processor processes information into a plurality of 8-level signaling symbols.  
     
     
         33 . A system for demodulating a received signal containing at least one of 4-level modulation and 8-level modulation, the system comprising: 
 a receiver for receiving said received signal;    a demodulator coupled to said receiver for operating under at least one of    a first assumption that said received signal contains 4-level modulation, wherein said demodulator operates as a constrained demodulator by restricting possible levels of said received signal to a set of four levels, determining which level out of said four levels is received, and produces 4-level signaling symbol decisions having 2-bits each, and    a second assumption that said received signal contains 8-level modulation, wherein said demodulator operates as an unconstrained demodulator by restricting possible levels of said received signal to a set of eight levels, determining which level out of said eight levels is received, and produces 8-level signaling symbol decisions having 3-bits each.    
     
     
         34 . The system of  claim 33  wherein said demodulator uses a maximum likelihood sequence estimation processor to demodulate said received signal.  
     
     
         35 . The system of  claim 33  further comprising a first error correction decoder coupled to said demodulator and a second error correction decoder coupled to said demodulator, wherein 
 when said demodulator is operating under said first assumption, said first error correction decoder decodes said 4-level signaling symbol decisions, and  
 when said demodulator is operating under said second assumption, said second error correction decoder decodes said 8-level signaling symbol decisions.  
 
     
     
         36 . The system of  claim 35  further comprising a controller coupled to said first and said second error correction decoders and to said demodulator wherein said first error correction decoder determines a first quality factor, said second error correction decoder determines a second quality factor, and 
 said controller uses said first and said second quality factors to determine whether 4-level modulation or 8-level modulation is present in said received signal, and 
 directs said demodulator to operate as said constrained demodulator if it is determined that 4-level signaling symbols are present in said received signal, and  
 directs said demodulator to operate as said unconstrained demodulator if it is determined that 8-level signaling symbols are present in said received signal.  
 
 
     
     
         37 . The system of  claim 33  further comprising a controller coupled to said demodulator wherein said controller determines whether 4-level modulation or 8-level modulation is present in said received signal, and 
 directs said demodulator to operate as said constrained demodulator if it is determined that 4-level signaling symbols are present in said received signal, and  
 directs said demodulator to operate as said unconstrained demodulator if it is determined that 8-level signaling symbols are present in said received signal.  
 
     
     
         38 . The system of  claim 37  wherein said controller uses at least one of an indication signal within said received signal and a predetermined transmission format to determine whether 4-level or 8-level modulation is present.  
     
     
         39 . The system of  claim 38  wherein said indication signal is encoded within at least one of a SYNCWORD, a CDVCC and a FACCH message.  
     
     
         40 . A system for decoding a signal containing at least one of 4-level modulation and 8-level modulation, the system comprising: 
 a receiver for receiving a signal;    a demodulator coupled to said receiver for demodulating said signal as 8-level modulation;    an error correction decoder coupled to said demodulator for performing error correction decoding under at least one of the assumptions that either: 
 4-level signaling symbols are present in said signal; or  
 8-level signaling symbols are present in said signal.  
   
     
     
         41 . The system of  claim 40  further comprising a controller coupled to said error correction decoder wherein said error correction decoder determines a first quality factor when operating under said first assumption, and said error correction decoder determines a second quality factor when operating under said second assumption, and 
 said controller determines a received modulation from said first and said second quality factors and sends a control signal to said error correction decoder to decode said signal as said received modulation.  
 
     
     
         42 . The system of  claim 41  wherein said controller determines said received modulation and sends said control signal to said error correction decoder before said decoding under said first and said second assumptions is complete.  
     
     
         43 . The system of  claim 41  wherein said error correction decoder further comprises a maximum likelihood sequence estimation processor wherein said error correction decoder determines said first and said second quality factors using metrics created by said maximum likelihood sequence estimator processor.  
     
     
         44 . The system of  claim 40  wherein said demodulator creates a symbol representing 3-bits and said error correction decoder removes a third bit from said 3-bits when performing error correction decoding under said second assumption.  
     
     
         45 . The system of  claim 40  further comprising a controller coupled to said decoder wherein said controller determines whether 4-level or 8-level signaling symbols are present in the demodulated signal, and 
 directs said error correction decoder to operate under the first assumption if it is determined that 4-level signaling symbols are present, or  
 directs said error correction decoder to operate under the second assumption if it is determined that 8-level signaling symbols are present.  
 
     
     
         46 . The system of  claim 45  wherein said controller uses at least one of an indication signal within said received signal and a predetermined transmission format to determine whether 4-level or 8-level signaling symbols are present.  
     
     
         47 . The system of  claim 46  wherein said indication signal is encoded within at least one of a SYNCWORD, a CDVCC and a FACCH message.