Pulse forming converter

Abstract

A scalable, interleaved pulse forming converter is disclosed having two Buck swithing converter modules each contributing half to the total load of the circuit to produce a programmable current pulse. Synchronization pulses to the two modules are set 180 degrees out of phase of each other to reduce ripple current. The invention is susceptible to various interleaved modifications to further reduce ripple current and increase power, as well as to electrically isolate the load from input or battery ground.

Having set forth the nature of the invention, what is claimed is:  
     
         1 . A circuit for providing an electrical pulse to a load, comprising: 
 a. a first Buck converter circuit;    b. a second Buck converter circuit connected to said first Buck converter circuit, each said Buck converter circuit adapted to receive a current command signal for establishing an internal reference voltage within each said Buck converter circuit;    c. means for applying a voltage across said first and said second Buck converter circuits;    d. a capacitor connected in parallel with said voltage means for reducing ripple in said voltage across said first and said second Buck converter circuits; and,    e. a synchronization controller operationally connected to each said Buck converter circuit for initiating electrical pulses in each said Buck converter circuit in interleaved fashion to produce a controllable pulse across said load.    
     
     
         2 . A pulse forming circuit as recited in  claim 1 , wherein each said Buck converter circuit is connected to a common load ground and wherein each said Buck converter circuit includes an isolated transistor driver.  
     
     
         3 . A pulse forming circuit as recited in  claim 2 , wherein said synchronization controller comprises an oscillator responsively enabled via an on/off command signal; a flip flop connected to an output of said oscillator, said flip flop including dual outputs; and a dual one-shot connected to said dual outputs of said flip flop for generating dual interleaved synchronization signal outputs to said two Buck converters.  
     
     
         4 . A pulse forming circuit as recited in  claim 1 , wherein each said Buck converter circuit has an isolated output such that said load is not grounded to said voltage means.  
     
     
         5 . A pulse forming circuit as recited in  claim 4 , wherein each said Buck converter circuit comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and operationally connected to said synchronization controller;    c. means operationally connected to said controller for sensing output current levels of said transistor;    d. an inductor operationally connected between said voltage means and said load; and,    e. a diode operationally connected to said voltage means and in parallel with said inductor to permit current flow through said load upon said transistor switching off.    
     
     
         6 . A pulse forming circuit as recited in  claim 5 , wherein said synchronization controller comprises an oscillator responsively enabled via an on/off command signal; a flip flop connected to an output of said oscillator, said flip flop including dual outputs; and a dual one-shot connected to said dual outputs of said flip flop for generating dual interleaved synchronization signal outputs to said two Buck converters.  
     
     
         7 . A pulse forming circuit as recited in  claim 1 , wherein each said Buck converter circuit comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and operationally connected to said synchronization controller;    c. means operationally connected to said controller for sensing output current levels of said transistor;    d. an inductor operationally connected between said voltage means and said load; and,    e. a diode operationally connected to said voltage means and in parallel with said inductor to permit current flow through said load upon said transistor switching off.    
     
     
         8 . A pulse forming circuit as recited in  claim 7 , wherein each said transistor controller comprises an RS flip flop connected to said transistor through its Q output; a comparator having inputs connected to said current sensing means and said current command signal, and having its output connected to an R input of said flip flop; and wherein said flip flop has its S input connected to said synchronization controller.  
     
     
         9 . A pulse forming circuit as recited in  claim 8 , wherein said synchronization controller comprises an oscillator responsively enabled via an on/off command signal; a divide by four circuit for dividing said oscillator output by four; a shift register operationally connected to an output of said divide by four circuit and adapted for outputting 1-N pulses in response to said oscillator output; and an N-phase one-shot circuit for receiving outputs from said shift register and outputting 1-N synchronization signals to each said Buck converter.  
     
     
         10 . A pulse forming circuit as recited in  claim 9 , further including additional 3 to N Buck converter circuits each connected to one another and each adapted to receive a current command signal for establishing an internal reference voltage, and each operationally connected to said synchronization controller for initiating electrical pulses in each said Buck converter circuit in interleaved fashion to produce a controllable pulse across said load.  
     
     
         11 . A pulse forming circuit as recited in  claim 10 , wherein said a load driving transistor comprises a power MOSFET.  
     
     
         12 . A pulse forming circuit as recited in  claim 10 , wherein said a load driving transistor comprises a field effect transistor.  
     
     
         13 . A pulse forming circuit as recited in  claim 10 , wherein said a load driving transistor comprises a bipolar transistor.  
     
     
         14 . A pulse forming circuit as recited in  claim 1 , wherein each said Buck converter circuit comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and operationally connected to said synchronization controller;    c. means operationally connected to said controller for sensing output current levels of said transistor;    d. means operationally connected between said voltage means and said load for inducing a current in said load upon switching said transistor off; and,    e. means operationally connected to said voltage means and in parallel with said induction means to provide a current flow path through said load upon said transistor switching off.    
     
     
         15 . A pulse forming circuit as recited in  claim 14 , wherein each said transistor controller comprises an RS flip flop connected to said transistor through its Q output; a comparator having inputs connected to said current sensing means and said current command signal, and having its output connected to an R input of said flip flop; and wherein said flip flop has its S input connected to said synchronization controller.  
     
     
         16 . A pulse forming circuit as recited in  claim 15 , wherein each said Buck converter circuit has an isolated output such that said load is not grounded to said voltage means.  
     
     
         17 . A pulse forming circuit as recited in  claim 1 , further including additional 3 to N Buck converter circuits each connected to one another and each adapted to receive a current command signal for establishing an internal reference voltage, and each operationally connected to said synchronization controller for initiating electrical pulses in each said Buck converter circuit in interleaved fashion to produce a controllable pulse across said load.  
     
     
         18 . A pulse forming circuit as recited in  claim 17 , wherein each said Buck converter circuit comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and operationally connected to said synchronization controller;    c. means operationally connected to said controller for sensing output current levels of said transistor;    d. an inductor operationally connected between said voltage means and said load; and,    e. a diode operationally connected to said voltage means and in parallel with said inductor to permit current flow through said load upon said transistor switching off.    
     
     
         19 . A pulse forming circuit as recited in  claim 18 , wherein each said transistor controller comprises an RS flip flop connected to said transistor through its Q output; a comparator having inputs connected to said current sensing means and said current command signal, and having its output connected to an R input of said flip flop; and wherein said flip flop has its S input connected to said synchronization controller.  
     
     
         20 . A circuit for providing an electrical pulse to a load, comprising: 
 a. first means for converting a voltage source into an electrical pulse;    b. second means connected to said first pulse means for converting a voltage source into an electrical pulse, each said pulse means adapted to receive a current command signal for establishing an internal reference voltage within each said pulse means;    c. means for applying a voltage across said first and said second pulse means;    d. means connected to said voltage means for reducing ripple in said voltage across said first and said second pulse means; and,    e. means connected to each said pulse means for initiating an electrical pulse in each said pulse means in synchronous interleaved fashion such that a pulse of desired characteristics is generated across said load.    
     
     
         21 . A pulse forming circuit as recited in  claim 20 , wherein each said pulse means comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and operationally connected to said synchronization means;    c. means operationally connected to said controller for sensing output current levels of said transistor;    d. means operationally connected between said voltage means and said load for inducing a current in said load upon switching said transistor off; and,    e. means operationally connected to said voltage means and in parallel with said induction means to provide a current flow path through said load upon said transistor switching off.    
     
     
         22 . A pulse forming circuit as recited in  claim 21 , wherein each said transistor controller comprises an RS flip flop connected to said transistor through its Q output; a comparator having inputs connected to said current sensing means and said current command signal, and having its output connected to an R input of said flip flop; and wherein said flip flop has its S input connected to said synchronization means.  
     
     
         23 . A pulse forming circuit as recited in  claim 22 , wherein said synchronization means comprises an oscillator responsively enabled via an on/off command signal; a divide by four circuit for dividing said oscillator output by four; a shift register operationally connected to an output of said divide by four circuit and adapted for outputting 1-N pulses in response to said oscillator output; and an N-phase one-shot circuit for receiving outputs from said shift register and outputting 1-N synchronization signals to each said pulse means.  
     
     
         24 . A pulse forming circuit as recited in  claim 23 , further including additional 3 to N Buck pulse means each connected to one another and each adapted to receive a current command signal for establishing an internal reference voltage, and each operationally connected to said synchronization means for initiating electrical pulses in each said pulse means in interleaved fashion to produce a controllable pulse across said load.  
     
     
         25 . A pulse forming circuit as recited in  claim 24 , wherein said a load driving transistor comprises a power MOSFET.  
     
     
         26 . A pulse forming circuit as recited in  claim 24 , wherein said a load driving transistor comprises a field effect transistor.  
     
     
         27 . A pulse forming circuit as recited in  claim 24 , wherein said a load driving transistor comprises a bipolar transistor.  
     
     
         28 . A pulse forming circuit as recited in  claim 20 , wherein each said pulse means comprises a converter circuit selected from the group consisting of Forward, Boost, Flyback, Push-Pull, Half-Bridge, Full-Bridge, Sepic, and Buck-Boost.  
     
     
         29 . A pulse forming circuit as recited in  claim 20 , further including additional 3 to N pulse means each connected to one another and each adapted to receive a current command signal for establishing an internal reference voltage, and each operationally connected to said synchronization means for initiating electrical pulses in each said pulse means in interleaved fashion to produce a controllable pulse across said load.  
     
     
         30 . A pulse forming circuit as recited in  claim 29 , wherein each said pulse means comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and operationally connected to said synchronization means;    c. means operationally connected to said transistor controller for sensing output current levels of said transistor;    d. an inductor operationally connected between said voltage means and said load; and,    e. a diode operationally connected to said voltage means and in parallel with said inductor to permit current flow through said load upon said transistor switching off.    
     
     
         31 . A pulse forming circuit as recited in  claim 30 , wherein each said transistor controller comprises an RS flip flop connected to said transistor through its Q output; a comparator having inputs connected to said current sensing means and said current command signal, and having its output connected to an R input of said flip flop; and wherein said flip flop has its S input connected to said synchronization means.  
     
     
         32 . A circuit for providing an electrical pulse to a load, comprising: 
 a. a first Buck converter circuit;    b. a second Buck converter circuit connected to said first Buck converter circuit, each said Buck converter circuit adapted to receive a current command signal for establishing an internal reference voltage within each said Buck converter circuit;    c. means for applying a voltage across said first and said second Buck converter circuits;    d. means connected to said voltage means for reducing ripple in said voltage across said first and said second Buck converter circuit; and,    e. wherein each said Buck converter circuit is adapted to receive an interleaved synchronization signal for initiating electrical pulses in each said Buck converter circuit to create a pulse of desired characteristics across said load.    
     
     
         33 . A pulse forming circuit as recited in  claim 32 , wherein each said Buck converter circuit has an isolated output such that said load is not grounded to said voltage means.  
     
     
         34 . A pulse forming circuit as recited in  claim 33 , wherein each said Buck converter circuit comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and adapted to receive said synchronization signal;    c. means operationally connected to said controller for sensing output current levels of said transistor;    d. an inductor operationally connected between said voltage means and said load; and,    e. a diode operationally connected to said voltage means and in parallel with said inductor to permit current flow through said load upon said transistor switching off.    
     
     
         35 . A pulse forming circuit as recited in  claim 34 , wherein each said Buck converter circuit is adapted for driving laser diode loads.  
     
     
         36 . A pulse forming circuit as recited in  claim 35 , wherein each said transistor controller comprises an RS flip flop connected to said transistor through its Q output; a comparator having inputs connected to said current sensing means and said current command signal, and having its output connected to an R input of said flip flop; and wherein said flip flop has its S input is adapted to receive said synchronization signal.  
     
     
         37 . A pulse forming circuit as recited in  claim 32 , further including additional 3 to N Buck converter circuits each connected to one another and each adapted to receive a current command signal for establishing an internal reference voltage and each adapted to receive said synchronization signal for initiating electrical pulses in each said Buck converter circuit in interleaved fashion to produce a controllable pulse across said load.  
     
     
         38 . A pulse forming circuit as recited in  claim 37 , wherein each said Buck converter circuit comprises: 
 a. a load driving transistor;    b. a controller operationally connected to said transistor for switching on said same, said controller adapted to receive said current command signal and adapted to receive said synchronization signal;    c. means operationally connected to said transistor controller for sensing output current levels of said transistor;    d. an inductor operationally connected between said voltage means and said load; and,    e. a diode operationally connected to said voltage means and in parallel with said inductor to permit current flow through said load upon said transistor switching off.    
     
     
         39 . A pulse forming circuit as recited in  claim 38 , wherein each said transistor controller comprises an RS flip flop connected to said transistor through its Q output; a comparator having inputs connected to said current sensing means and said current command signal, and having its output connected to an R input of said flip flop; and wherein said flip flop has its S input adapted to receive said synchronization signal.  
     
     
         40 . A circuit for providing an electrical pulse to a load, comprising: 
 a. first means for converting a voltage source into an electrical pulse;    b. second means connected to said first pulse means for converting a voltage source into an electrical pulse, each said pulse means adapted to receive a current command signal for establishing an internal reference voltage within each said pulse means;    c. means for applying a voltage across said first and said second pulse means;    d. means connected to said voltage means for reducing ripple in said voltage across said first and said second pulse means; and,    e. each said pulse means adapted to receive an interleaved synchronization signal for initiating electrical pulses in each said pulse means to create a pulse of desired characteristics across said load.    
     
     
         41 . A pulse forming circuit as recited in  claim 40 , wherein each said Buck converter circuit comprises: 
 a. means for driving a load;    b. a controller operationally connected to said load driving means for switching on said same, said controller adapted to receive said current command signal and adapted to receive said synchronization signal;    c. means operationally connected to said controller for sensing output current levels of said load driving means;    d. means operationally connected between said voltage means and said load for inducing a current in said load upon switching said load driving means off; and,    e. means operationally connected to said voltage means and in parallel with said induction means to provide a current flow path through said load upon said load driving means switching off.    
     
     
         42 . A pulse forming circuit as recited in  claim 41 , further including additional 3 to N pulse means each connected to one another and each adapted to receive a current command signal for establishing an internal reference voltage and each adapted to receive said synchronization signal for initiating electrical pulses in each said pulse means in interleaved fashion to produce a controllable pulse across said load.  
     
     
         43 . A pulse forming circuit as recited in  claim 42 , wherein each said pulse means is adapted for driving laser diode loads.  
     
     
         44 . A pulse forming circuit as recited in  claim 43 , wherein each said pulse means has an isolated output such that said load is grounded separately from said voltage means.  
     
     
         45 . A pulse forming circuit as recited in  claim 44 , wherein each said pulse means is connected to a common load ground and wherein each said driving means is isolated from said load.  
     
     
         46 . A pulse forming circuit as recited in  claim 40 , wherein each said pulse means comprises a converter circuit selected from the group consisting of Forward, Boost, Flyback, Push-Pull, Half-Bridge, Full-Bridge, Sepic, and Buck-Boost.  
     
     
         47 . A pulse forming circuit as recited in  claim 40 , further including additional 3 to N pulse means each connected to one another and each adapted to receive a current command signal for establishing an internal reference voltage and each adapted to receive said synchronization signal for initiating electrical pulses in each said pulse means in interleaved fashion to produce a controllable pulse across said load.  
     
     
         48 . A pulse forming circuit as recited in  claim 47 , wherein said driving means comprises a solid-state power switch.  
     
     
         49 . A method for creating an electrical pulse across a load, comprising the steps of: 
 a. applying a voltage across at least two connected Buck converter circuits;    b. providing a reference voltage to control output pulse amplitude for each said Buck converter circuits;    c. applying a synchronization signal in an interleaved manner to each said Buck converter; and,    d. initiating a pulse from each Buck converter responsive to said synchronization pulse for a specified duration such that a pulse of controllable quality is generated across said load.    
     
     
         50 . A method as recited in  claim 49 , wherein said step of initiating a pulse from each Buck converter further comprises controllably summing each pulse generated by each Buck converter to produce a pulse across said load of desirable quality.  
     
     
         51 . A method as recited in  claim 50 , wherein said step of initiation of a pulse from each Buck converter comprises: 
 a. receiving said synchronization signal into a control element;    b. turning on a load driving element responsive to said reception of said synchronization signal to generate current across said load;    c. sensing current level in an output of said load driving element and generating a current level signal responsive thereof;    d. comparing said current level signal to a reference signal sent to said Buck converter and generating a signal responsive thereof;    e. turning off said load driving element conditionally responsive to said signal generated in said comparing step; and,    f. repeating steps a-e to produce a train of desired pulses from said Buck converter.    
     
     
         52 . A method as recited in  claim 51 , wherein said step of providing a reference voltage to said Buck converter comprises: 
 a. initiating an oscillator in response to an on/off command signal;    b. receiving a signal into a shifting capable memory element capable of outputting 1-N signals where N is equal to the number of existing Buck converter circuits responsive to signals sent by said oscillator; and,    c. receiving outputs from said shifting capable memory element and issuing synchronization signals from a one-shot circuit element to each of said Buck converters.    
     
     
         53 . A method for creating an electrical pulse across a load, comprising the steps of: 
 a. applying a voltage across at least two connected circuits capable of generating a pulse across a load;    b. providing a reference voltage to control output pulse amplitude for each said pulse circuit;    c. applying a synchronization signal in an interleaved manner to each said pulse circuit; and,    d. initiating a pulse from each pulse circuit responsive to said synchronization pulse for a specified duration such that a pulse of controllable quality is generated across said load.    
     
     
         54 . A method as recited in  claim 53 , wherein said step of initiating a pulse from each pulse circuit further comprises controllably summing each pulse generated by each pulse circuit to produce a pulse across said load of desirable quality.  
     
     
         55 . A method as recited in  claim 54 , wherein said step of initiation of a pulse from each pulse circuit comprises: 
 a. receiving said synchronization signal into a control element;    b. turning on a load driving element responsive to said reception of said synchronization signal to generate current across said load;    c. sensing current level in an output of said load driving element and generating a current level signal responsive thereof;    d. comparing said current level signal to a reference signal sent to said pulse circuit and generating a signal responsive thereof;    e. turning off said load driving element conditionally responsive to said signal generated in said comparing step; and,    f. repeating steps a-e to produce a train of desired pulses from said pulse circuit.    
     
     
         56 . A method as recited in  claim 55 , wherein said step of providing a reference voltage to said pulse circuit comprises: 
 a. initiating an oscillator in response to an on/off command signal;    b. receiving a signal into a shifting capable memory element capable of outputting 1-N signals where N is equal to the number of existing pulse circuits responsive to signals sent by said oscillator; and,    c. receiving outputs from said shifting capable memory element and issuing synchronization signals from a one-shot circuit element to each of said pulse circuits.