Semiconductor device and method for manufacturing the same

Abstract

Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an isolation insulating film, an epitaxial silicon layer, a junction blocking insulating film, a gate stack, and source and drain junctions. The isolation insulating film is formed on a semiconductor substrate to define an active area. The epitaxial silicon layer is formed in the active area of the semiconductor substrate and surrounded by the isolation insulating film. The junction blocking insulating film is formed in the epitaxial silicon layer. The gate stack is formed over the epitaxial silicon layer so that the junction blocking insulating film is buried under approximately the center of the gate stack. The source and drain junctions are formed adjacent the sidewalls of the gate stack. Accordingly, a short circuit between source/drain junctions in a bulk area caused by the unwanted diffusion of the junctions can be prevented.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 an isolation insulating film formed in a semiconductor substrate to define an active area;    an epitaxial silicon layer formed in the active area and surrounded by the isolation insulating film;    a gate stack formed over the epitaxial silicon layer;    a junction blocking insulating film vertically extending in the epitaxial silicon layer and disposed under the gate stack; and    source and drain junctions formed adjacent sidewalls of the gate stack.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the junction blocking insulating film divides the active area into two areas.  
     
     
         3 . The semiconductor device of  claim 1 , wherein the junction blocking insulating film is disposed under approximately the center of the gate stack.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the isolation insulating film is one of a silicon oxide film and a silicon nitride film.  
     
     
         5 . The semiconductor device of  claim 1 , wherein the junction blocking insulating film is one of a silicon oxide film and a silicon nitride film.  
     
     
         6 . The semiconductor device of  claim 1 , wherein the isolation insulating film and the junction blocking insulating film are formed of an identical film.  
     
     
         7 . The semiconductor device of  claim 1 , wherein the gate stack comprises: 
 a gate dielectric layer formed on the epitaxial silicon layer;    a gate conductive layer formed on the gate dielectric layer; and    insulating spacers formed on sidewalls of the gate conductive layer.    
     
     
         8 . The semiconductor device of  claim 7 , wherein the gate conductive layer comprises a metal silicide layer.  
     
     
         9 . The semiconductor device of  claim 7 , wherein the gate stack further comprises a mask insulating layer formed on the gate conductive layer.  
     
     
         10 . A method for manufacturing a semiconductor device, the method comprising: 
 (a) forming an isolation insulating film on a semiconductor substrate;    (b) removing a portion of the isolation insulating film to a predetermined depth;    (c) forming a mask insulating layer on the isolation insulating film;    (d) patterning the mask insulating layer and the isolation insulating film, to form an isolation structure that defines an active area and to form a junction blocking insulating film in the active area;    (e) forming an epitaxial silicon layer in the active area such that the junction blocking insulating film is buried in the eptiaxial silicon layer;    (f) forming a gate stack on the epitaxial silicon layer; and    (g) forming source and drain junctions in the epitaxial silicon layer.    
     
     
         11 . The method of  claim 10 , wherein the isolation insulating film is a silicon oxide film.  
     
     
         12 . The method of  claim 10 , wherein the isolation insulating film is formed using chemical vapor deposition (CVD).  
     
     
         13 . The method of  claim 10 , wherein the isolation insulating film is formed by oxidizing the semiconductor substrate.  
     
     
         14 . The method of  claim 10 , wherein step (b) comprises: 
 forming a photoresist pattern that defines the active area over the isolation insulating film;    dry etching the isolation insulating film to a predetermined depth using the photoresist pattern as a mask; and    removing the photoresist pattern.    
     
     
         15 . The method of  claim 10 , wherein in step (c), the mask insulating layer is formed of a material different than a material forming the isolation insulating film.  
     
     
         16 . The method of  claim 10 , wherein the mask insulating layer is a silicon nitride layer.  
     
     
         17 . The method of  claim 10 , wherein step (d) comprises: 
 forming a photoresist pattern on the mask insulating layer;    dry etching the mask insulating layer and the isolation insulating film, using the photoresist pattern as a mask; and    removing the photoresist pattern.    
     
     
         18 . The method of  claim 10 , wherein step (e) comprises: 
 (e-1) removing the isolation insulating layer remaining in the active area; and    (e-2) forming the epitaxial silicon layer in the active area by selective epitaxial growth (SEG), using the isolation insulating film and the junction blocking insulating film as masks.    
     
     
         19 . The method of  claim 18 , wherein step (e-2) uses the substrate in the active area as a source for SEG.  
     
     
         20 . The method of  claim 18 , wherein step (e-2) comprises: 
 growing the epitaxial silicon layer thicker than the isolation insulating layer; and    planarizing the epitaxial silicon layer to a top surface of the isolation insulating film.    
     
     
         21 . The method of  claim 20 , wherein the planarization process is performed, using chemical mechanical polishing (CMP).  
     
     
         22 . The method of  claim 20 , wherein the planarization process is performed, using the isolation insulating film as a polishing stopper.  
     
     
         23 . The method of  claim 10 , wherein step (f) comprises: 
 forming a gate dielectric layer on the eptiaxial silicon layer;    forming a gate conductive layer on the gate dielectric layer; and    forming a gate pattern on the gate conductive layer so that a portion of the epitaxial silicon layer on the junction blocking insulating film is disposed under approximately the center of the gate stack in the active area.    
     
     
         24 . The method of  claim 23 , wherein the gate dielectric layer is one of a silicon oxide layer and an oxynitride layer.  
     
     
         25 . The method of  claim 23 , wherein the gate conductive layer comprises at least one of doped polysilicon and metal silicide.  
     
     
         26 . The method of  claim 23 , further comprising, after the gate pattern is formed, forming insulating spacers on sidewalls of the gate conductive layer.  
     
     
         27 . The method of  claim 10 , wherein step (g) comprises: 
 doping junction ions, using the gate stack as a mask; and    diffusing the junction ions, using a predetermined thermal process.    
     
     
         28 . The method of  claim 27 , wherein the junction ions are P-type impurity or N-type impurity.  
     
     
         29 . The method of  claim 28 , wherein the P-type impurity is boron (B) or BF 2 .  
     
     
         30 . The method of  claim 28 , wherein the N-type impurity is phosphorus (P), arsenic (As), or antimony.  
     
     
         31 . A method for manufacturing a semiconductor device, the method comprising: 
 forming an isolation structure that defines an active area and forming a junction blocking insulating film in the active area, on a semiconductor substrate; and    forming an epitaxial silicon layer in the active area such that the junction blocking insulating film is buried in the eptiaxial silicon layer.    
     
     
         32 . The method of  claim 31 , further comprising: 
 forming a gate stack on the epitaxial silicon layer; and    forming source and drain junctions in the epitaxial silicon layer.    
     
     
         33 . The method of  claim 3   1 , wherein forming an isolation structure comprises: 
 forming an isolation insulating film on the semiconductor substrate;    removing a portion of the isolation insulating film to a predetermined depth;    forming a mask insulating layer on the isolation insulating film; and    patterning the mask insulating layer and the isolation insulating film.