Buffer, buffer operation and method of manufacture

Abstract

An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

What is claimed is:  
     
         1 . An integrated circuit comprising: 
 a MOSFET having a drain region of a first conductivity type; and    a JFET integrated with a portion of the drain region of the MOSFET.    
     
     
         2 . An integrated circuit according to  claim 1 , in which 
 the JFET comprises a gate of second conductivity type in contact with material of the first conductivity type associated with the drain region; and    the gate of the JFET operable under bias to apply an electric field to and to affect depletion of carriers within a region of the material of the first conductivity type proximate the gate of the JFET.    
     
     
         3 . An integrated circuit according to  claim 2 , in which the gate of the JFET comprises a well of second conductivity type within the drain region of the MOSFET.  
     
     
         4 . An integrated circuit according to  claim 3 , in which the JFET comprises a channel region of the first conductivity type contiguous with the drain region.  
     
     
         5 . An integrated circuit according to  claim 3 , further comprising: 
 dielectric over the well of the second conductivity type; and    conductive material over the dielectric.    
     
     
         6 . An integrated circuit according to  claim 3 , further comprising conductive material in insulated relationship over the well of the second conductivity type.  
     
     
         7 . An integrated circuit according to  claim 6 , further comprising dielectric between the conductive material and the well of the second conductivity type.  
     
     
         8 . A semiconductor device comprising: 
 a substrate of a first conductivity type;    first and second wells of second conductivity type in the substrate;    conductive material over a channel region of the substrate between the first and second wells;    the conductive material operable under bias to apply an electric field to the channel region of the substrate to enhance carriers therein between the first and second wells; and    a third well of first conductivity type within the first well;    the third well operable to receive a bias to apply an electric field to a depletion region of the first well and operable for depletion of carriers within the depletion region.    
     
     
         9 . A semiconductor device according to  claim 8 , in which the depletion region is a contiguous portion of the first well proximate the third well.  
     
     
         10 . A semiconductor device according to  claim 8 , further comprising dielectric between the substrate and the conductive material.  
     
     
         11 . A semiconductor device according to  claim 10 , further comprising: 
 dielectric over the third well; and    conductive material over the dielectric and capacitively coupled to the third well;    the channel region of the substrate operable as an enhancement channel; and    the conductive material capacitively coupled to the third well separate from the conductive material over the channel region of the substrate.    
     
     
         12 . A semiconductor device according to  claim 8 , further comprising: 
 a drain contact to the first well;    the third well operable under the bias to adjust a series resistance of the first well between the drain contact and the enhancement channel region.    
     
     
         13 . A semiconductor device according to  claim 1   1 , further comprising conductive material over and capacitively coupled to the third well.  
     
     
         14 . A circuit comprising: 
 an N-MOSFET;    a P-MOSFET comprising a channel electrically coupled in series with that of the N-MOSFET; and    a JFET comprising a channel electrically coupled in series between the channels of the N-MOSFET and the P-MOSFET.    
     
     
         15 . A circuit according to  claim 14 , further comprising; 
 an output terminal;    the MOSFETs operable to drive the output terminal;    the JFET comprising a gate to affect an output impedance presented to the output terminal dependent on a voltage bias of the gate.    
     
     
         16 . A circuit according to  claim 15 , in which the JFET is electrically coupled between the drains of the MOSFETs; and 
 the output terminal is electrically coupled to the drain of the P-channel MOSFET.    
     
     
         17 . A circuit according to  claim 16 , in which the N-MOSFET comprises a vertical drain MOSFET structure.  
     
     
         18 . A circuit according to  claim 17 , in which the JFET comprises a channel region contiguous with the drain region of the N-channel MOSFET.  
     
     
         19 . A circuit according to  claim 18 , in which the JFET comprises a gate operable to affect a propagation direction for carriers traversing the drain region of the N-channel MOSFET and to establish a vertical drain characteristic of the N-MOSFET.  
     
     
         20 . A circuit according to  claim 14 , further comprising a programmable voltage source to drive a gate of the JFET.  
     
     
         21 . A circuit according to  claim 20 , further comprising a capacitor to electrically couple signal transients to the gate of the JFET.  
     
     
         22 . A circuit according to  claim 20 , further comprising: 
 an output terminal;    the MOSFETS to drive the output terminal;    the JFET between the output terminal and one of the MOSFETs; and    the capacitor to capacitively couple a signal of the output terminal to the gate of the JFET.    
     
     
         23 . A circuit according to  claim 22 , in which the JFET comprises a channel contiguous with the drain region of one of the MOSFETs.  
     
     
         24 . A circuit according to  claim 20 , further comprising: 
 a pre-driver selectably operable to drive the gate of the P-MOSFET with one of a level shifted representation of an input signal or a second signal of a magnitude up to disable the P-MOSFET; and    a threshold circuit to control operation of the pre-driver based on the level of a signal at the output node.    
     
     
         25 . A circuit according to  claim 24 , in which the threshold circuit selects the operation of the pre-driver based on a comparison of the level of the signal at the output with respect to a predetermined threshold.  
     
     
         26 . A method of driving an output node, comprising: 
 using an enhancement channel MOSFET to drive the output node;    driving the gate of the enhancement channel MOSFET dependent on an input signal; and    applying an electric field to a portion of the drain region of the MOSFET to deplete at least some carriers within the portion of the drain region.    
     
     
         27 . A method according to  claim 26 , in which the applying an electric field pinches a conductive path of the drain region to affect a resistance of the drain region of the MOSFET.  
     
     
         28 . A method according to  claim 26 , further comprising: 
 monitoring a level of a signal at the output node; and    adjusting a magnitude of the electric field by which to affect the resistance of the drain of the MOSFET dependent on the monitoring.    
     
     
         29 . A method according to  claim 26 , in which 
 the applying the electric field affects the conductive passage of the JFET channel and influences the series drain resistance of the MOSFET;    biasing a gate region of the JFET in contact with the conductive channel to establish the electric field.    
     
     
         30 . A method of forming an integrated circuit, comprising: 
 forming a MOSFET;    forming a gate for a JFET effective to modulate a depletion channel thereof, the depletion channel contiguous with a drain region of the MOSFET; and    configuring a programmable source to drive the gate of the JFET with a given voltage.    
     
     
         31 . A method according to  claim 30 , further comprising determining a V-I characteristic of the MOSFET; 
 the configuring to program the programmable source based on a determined V-I characteristic from the determining.    
     
     
         32 . A method according to  claim 30 , further comprising: 
 determining an impedance of the MOSFET; and    establishing the given bias voltage for the configuring dependent on the determined impedance.    
     
     
         33 . A method according to  claim 30 , in which 
 the forming the MOSFET comprises forming a drain region of first conductivity type for the MOSFET in a semiconductor substrate of second conductivity type;    the forming the drain region comprises implanting dopants of first conductivity type to form a well thereof within the semiconductor substrate of second conductivity type; and    the forming the JFET comprises forming a well of the second conductivity type within a portion of the well of first conductivity type.    
     
     
         34 . A method according to  claim 33 , farther comprising coupling the well of the second conductivity type as the gate of the JFET to the programmable source.  
     
     
         35 . A method according to  claim 34 , further comprising capacitively coupling the well of the second conductivity type to the programmable source.  
     
     
         36 . A buffer comprising: 
 a first MOSFET comprising a channel serially coupled between an output node and a first voltage node;    a second MOSFET comprising a channel serially coupled between the output node and a second voltage node;    a pre-driver operable to drive a gate of the first MOSFET with a select one of a first or second signal;    the pre-driver operable to level shift a data signal to establish the first signal; and    a determining circuit operable to affect the select operation of the pre-driver based on the level of signals at the output node.    
     
     
         37 . A buffer according to  claim 36 , the determining circuit to determine when the level of a signal at the output exceeds a predetermined threshold and to establish the pre-driver select operation based upon the threshold determination.  
     
     
         38 . A buffer according to  claim 37 , the determining circuit to determine when the level of a signal at the output is greater than the voltage of the first voltage node relative the second voltage node; and 
 the determining circuit to establish the second signal of magnitude up to that of the first voltage node for the select operation of the pre-driver when the determining determines the level of the signal at the output node to be greater than the voltage at the first node.    
     
     
         39 . A buffer according to  claim 36 , in which the first and the second MOSFETs each comprise N-channel MOSFETs.  
     
     
         40 . A method of operating a buffer coupled to an output node, comprising: 
 monitoring a voltage level of the output node; and    tri-stating the buffer when the voltage level of the output node exceeds a pull-up voltage within the buffer.    
     
     
         41 . A method according to  claim 40 , in which the tri-stating comprises disabling at least one pull-up MOSFET associated with driving the output node when the voltage of the output node is greater than the pull-up voltage within the buffer.  
     
     
         42 . A method according to  claim 41 , in which the disabling comprises driving the gate of an N-channel MOSFET s the pull-up MOSFET with a voltage less than the pull-up voltage.  
     
     
         43 . A data processing system comprising: 
 a processor;    a bus coupled to the processor;    an I/O buffer to interface a communication line of the processor to the bus, the I/O buffer comprising: 
 a pull-down MOSFET to drive the bus;  
 the pull-down MOSFET having a drain region; and  
 a JFET having a depletion channel contiguous with the drain region of the pull-down MOSFET.  
   
     
     
         44 . A data processing system according to  claim 43 , the depletion channel of the JFET electrically in series between the channel of the pull-down MOSFET and the output node.  
     
     
         45 . A data processing system according to  claim 44 , in which 
 the drain of the pull-down MOSFET comprises a well of a first conductivity type implanted in a substrate of second conductivity type; and    a gate region of the JFET comprises a well of second conductivity type implanted in a portion of the well for the drain of the MOSFET.    
     
     
         46 . A data processing system according to  claim 45 , further comprising: 
 a programmable source to drive the gate region of the JFET with a given bias; and    a pre-driver to drive a gate of the MOSFET separately from the gate of the JFET.