Semiconductor device

Abstract

A semiconductor device includes: a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type; a first main electrode connected to the low-resistance drain layer; a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer; a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer; a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer; a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate; a jfet layer of the first conductivity type formed on side walls of the trench; an insulating layer formed in the trench; an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to the first-conductivity type jfet layer around a top face of the trench; a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of the LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across the trench, and on a region of the surface of the second-conductivity type base layer sandwiched by the LDD layer and the first-conductivity type source layer; and a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;    a first main electrode connected to the low-resistance drain layer;    a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer;    a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer;    a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;    a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layers in a surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer;    a gate insulating film formed on at least a part of the surface of said first-conductivity type jfet layer, on the surfaces of the second-conductivity type base layers facing each other across said first-conductivity type jfet layer, and on the surfaces of end portions of the first-conductivity type source layers facing each other across said first-conductivity type jfet layer;    a control electrode formed on the gate insulating film; and    a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode,    wherein assuming that depth of the second-conductivity type base layer is Xj, width L of said first-conductivity type jfet layer in the direction orthogonal to the longitudinal direction of the control electrode is substantially equal to or less than that of an interval between neighboring control electrodes and satisfies the following expression.      L≦Xj× 0.7    
     
     
         2 . The semiconductor device according to  claim 1 , wherein depth of said first-conductivity type jfet layer is substantially same as that of the second-conductivity type base layer.  
     
     
         3 . The semiconductor device according to  claim 1 , wherein impurity concentration N of said first-conductivity type jfet layer satisfies the following expression.  
         N≦ 4 E 12 /L  [cm −3 ] 
     
     
         4 . The semiconductor device according to  claim 1 , wherein a junction interface between the second-conductivity type base layer and said first-conductivity type jfet layer becomes perpendicular to the surface of the device as it comes close to the surface of the device.  
     
     
         5 . The semiconductor device according to  claim 1 , wherein at least a part of a region of the gate insulating film facing said first-conductivity type jfet layer is thicker than the other region of the gate insulating film.  
     
     
         6 . The semiconductor device according to  claim 1 , wherein the gate insulating film and the control electrode are formed by selectively removing a part of a region facing said first-conductivity type jfet layer.  
     
     
         7 . The semiconductor device according to  claim 6 , wherein said first-conductivity type jfet layer is formed in a self-aligned manner by using the control electrode as a mask.  
     
     
         8 . The semiconductor device according to  claim 6 , which further comprises a first-conductivity type LDD layer which is formed in a surface portion of said first-conductivity type jfet layer and impurity concentration of which is higher than that of the high-resistance epitaxial layer and is lower than that of said first-conductivity type jfet layer.  
     
     
         9 . The semiconductor device according to  claim 8 , wherein said first-conductivity type LDD layer is formed in a self-aligned manner by using the control electrode as a mask.  
     
     
         10 . The semiconductor device according to  claim 6 , wherein surface peak concentration of said first-conductivity type jfet layer is 5E17 [cm −3  ] or less.  
     
     
         11 . The semiconductor device according to  claim 6 , wherein said first-conductivity type jfet layers each having a rectangular plane shape are disposed at regular intervals in the longitudinal direction of the control electrode, and the second-conductivity type base layer is formed so as to surround each of said first-conductivity type jfet layers.  
     
     
         12 . The semiconductor device according to  claim 6 , wherein said first-conductivity type jfet layers each having a circular plane shape are disposed at regular intervals in the longitudinal direction of the control electrode, and the second-conductivity type base layer is formed so as to surround each of said first-conductivity type jfet layers.  
     
     
         13 . The semiconductor device according to  claim 6 , wherein said first-conductivity type jfet layers each having a polygonal plane shape are disposed at regular intervals in the longitudinal direction of the control electrode, and the second-conductivity type base layer is formed so as to surround each of said first-conductivity type jfet layers.  
     
     
         14 . A semiconductor device comprising: 
 a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;    a first main electrode connected to the low-resistance drain layer;    a high-resistance epitaxial layer of the first conductivity type formed on the low-resistance drain layer;    a second-conductivity type base layer selectively formed in a surface portion of the high-resistance epitaxial layer;    a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;    a jfet layer of the first conductivity type selectively formed in a region sandwiched by the second-conductivity type base layer in the surface portion of the high-resistance epitaxial layer and having impurity concentration higher than that of the high-resistance epitaxial layer;    a gate insulating film formed on at least a part of the surface of said first-conductivity type jfet layer, on the surfaces of the second-conductivity type base layers facing each other across said first-conductivity type jfet layer, and on the surfaces of end portions of the first-conductivity type source layers facing each other across said first-conductivity type jfet layer;    a control electrode formed on the gate insulating film; and;    a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode,    wherein the second-conductivity type base layers sandwiching said first-conductivity type jfet layer are disposed close to each other so that depletion from the second-conductivity type base layer becomes dominant, and    the gate insulating film and the control electrode are formed by selectively removing a part of a region facing said first-conductivity type jfet layer.    
     
     
         15 . The semiconductor device according to  claim 14 , which further comprises an insulating layer formed in said first-conductivity type jfet layer.  
     
     
         16 . The semiconductor device according to  claim 15 , which further comprises an electrode which is formed in the insulating layer so as to be covered with the insulating layer and to which a potential is fixed.  
     
     
         17 . The semiconductor device according to  claim 16 , wherein an electrode in said first-conductivity type jfet layer is connected to the second main electrode.  
     
     
         18 . A semiconductor device comprising: 
 a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;    a first main electrode connected to the low-resistance drain layer;    a high-resistance epitaxial layer of a second-conductivity type formed on the low-resistance drain layer;    a second-conductivity type base layer selectively formed on the high-resistance epitaxial layer;    a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;    a trench formed in a region sandwiched by the second-conductivity type base layers with a depth extending from the surface of the high-resistance epitaxial layer to the semiconductor substrate;    a jfet layer of the first conductivity type formed on side walls of said trench;    an insulating layer formed in said trench;    an LDD layer of the first-conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to said first-conductivity type jfet layer around a top face of said trench;    a control electrode formed above the semiconductor substrate so as to be divided into a plurality of parts, and formed on a gate insulating film formed on a part of the surface of said LDD layer, on surfaces of end parts of the first-conductivity type source layer facing each other across said trench, and on a region of the surface of the second-conductivity type base layer sandwiched by said LDD layer and the first-conductivity type source layer; and    a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.    
     
     
         19 . The semiconductor device according to  claim 18 , which further comprises an electrode which is formed in said trench so as to be covered with the insulating layer and to which a potential is fixed.  
     
     
         20 . A semiconductor device comprising: 
 a semiconductor substrate, at least a surface portion thereof serving as a low-resistance drain layer of a first conductivity type;    a first main electrode connected to the low-resistance drain layer;    a first insulating layer formed on the low-resistance drain layer;    a second-conductivity type base layer formed on the first insulating layer;    a first-conductivity type source layer selectively formed in a surface portion of the second-conductivity type base layer;    a trench formed so as to extend from the surface of the second-conductivity type base layer to the semiconductor substrate;    a jfet layer of the first conductivity type formed on side walls of said trench;    a second insulating layer formed in said trench;    an LDD layer of the first conductivity type formed in a surface portion of the second-conductivity type base layer so as to be connected to said jfet layer of the first conductivity type around a top face of said trench;    a control electrode formed so as to be divided into a plurality of parts above the semiconductor substrate, and formed on a gate insulating film formed on a part of the surface of said LDD layer, on surfaces of end portions of the first-conductivity type source layer facing each other across said trench, and on a region of the second-conductivity type base layer sandwiched by said LDD layer and the first-conductivity type source layer; and    a second main electrode in ohmic contact with the first-conductivity type source layer and the second-conductivity type base layer so as to sandwich the control electrode.    
     
     
         21 . The semiconductor device according to  claim 20 , which further comprises an electrode which is formed in the second insulating layer so as to be covered with the second insulating layer and to which a potential is fixed.