Low power level-sensitive scan mechanism

Abstract

A latch suitable for an integrated circuit having a test mechanism that involves scanning a set of logic circuits has a two-stage main latch and a level-sensitive scan latch, the combination operating normally as a single-phase latch and as a master-slave latch during scan mode. The scan mechanism is introduced at the second stage of the main latch, with the result that the capacitance introduced by the scan connection switches at most once per clock cycle, reducing the power load of the circuit; and the scan latch output is separated from the data output of the main latch, thereby further reducing the power load.

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is:  
     
         1 . A scannable latch comprising a main latch and a scan latch for controllably passing data down at least one scan chain during a scan mode, said main latch having a data input terminal, a data out terminal, at least one clock terminal, a scan in terminal and a scan control terminal said main latch further comprising: 
 a memory subcircuit for holding data at said data output terminal that switches at most once per clock cycle during the normal operation mode;    a data control subcircuit connected to said data input terminal for overwriting the state of said memory subcircuit in response to a signal on said data input; and    a scan control subcircuit responsive to said scan input terminal and said scan control terminal for overwriting the state of said memory subcircuit in response to a scan control signal and connected directly to said memory subcircuit, whereby the introduced capacitance of said scan control subcircuit switches at most once per clock cycle during the normal operation mode.    
     
     
         2 . A scannable latch comprising a main latch and a scan latch for controllably passing data from a scan out terminal down at least one scan chain during a scan mode, said main latch having a data in terminal, at least one data out terminal electrically separated from said scan out terminal, at least one clock terminal, scan in terminal and scan control terminal in which said main latch consists of a memory subcircuit connected to said data output terminal of the latch, said scan in terminal and said scan control terminal for holding data at said data output of the latch that switches at most once in one clock cycle during the normal operation mode and which has means for changing the state of said data in response to transitions at said scan input and scan control terminals, so that the parasitic capacitance of transistors that change the state of said memory subcircuit switches at most once per clock cycle during the normal operation mode, thereby reducing the power overhead of the scan mechanism; and a subcircuit connected to the said data input of the latch and one or two said clock inputs for overwriting the state of said memory subcircuit in response to appropriate transitions at the said data and clock input terminals.  
     
     
         3 . A latch according to  claim 1  in which said data control subcircuit and said memory subcircuit are configured to operate as a single-phase latch in the normal mode, and in which said scan control and memory subcircuits and said scan latch are configured to operate as a master-slave latch during said scan mode.  
     
     
         4 . A latch according to  claim 2 , in which said data control subcircuit and said memory subcircuit are configured to operate as a single-phase latch in the normal mode, and in which said memory subcircuit and said scan latch are configured to operate as a master-slave latch during said scan mode.  
     
     
         5 . A latch according to  claim 3 , in which said scan control and memory subcircuits and said scan latch are configured to operate during said scan mode as a master-slave latch with two nonoverlapping clocks.  
     
     
         6 . A latch according to  claim 4 , in which said memory subcircuit and said scan latch are configured to operate during said scan mode as a master-slave latch with two nonoverlapping clocks.  
     
     
         7 . A latch according to  claim 1  in which said data control subcircuit and said memory subcircuit are configured to operate as a two-phase master-slave latch in the normal mode, and in which said scan control and memory subcircuits and said scan latch are configured to operate as a master-slave latch during said scan mode.  
     
     
         8 . A latch according to  claim 2  in which said data control subcircuit and said memory subcircuit are configured to operate as a two-phase master-slave latch in the normal mode, and in which said memory subcircuit and said scan latch are configured to operate as a master-slave latch during said scan mode.  
     
     
         9 . A latch according to  claim 1  in which said data control subcircuit and said memory subcircuit are configured to operate as a pulsed latch, and in which said scan control and memory subcircuits and said scan latch are configured to operate as a master-slave latch during said scan mode.  
     
     
         10 . A latch according to  claim 2  in which said data control subcircuit and said memory subcircuit are configured to operate as a pulsed latch, and in which said memory subcircuit and said scan latch are configured to operate as a master-slave latch during said scan mode.