Top gate thin-film transistor and method of producing the same

Abstract

A method of producing a top gate thin-film transistor in which an insulated gate structure ( 14 ) is formed over an amorphous silicon layer with upper gate conductor ( 16 ) directly over the gate insulator layers. The gate conductor is patterned to be narrower than a spacing to be provided between source and drain electrode contacts. Laser annealing of areas of the amorphous silicon layer ( 12 ) not shielded by the gate conductor ( 16 ) is carried out to form polysilicon portions. The gate insulator layers are formed as a gate insulator layer ( 14 a, 14 b ) of first refractive index, and an overlying surface insulator layer ( 14 c ) of second, lower, refractive index. The overlying surface insulator layer has been found to reduce fluctuations in the reflectance of the structure in dependence upon the specific thicknesses of the gate insulator layers. Therefore, the tolerances for the thicknesses of the gate insulator layers can be reduced whilst maintaining control of the laser annealing process.

1 . A method of producing a top gate thin-film transistor, comprising the steps of: 
 forming an amorphous silicon layer over an insulating substrate;    forming an insulated gate structure over the amorphous silicon layer comprising gate insulator layers and an upper gate conductor directly over the gate insulator layers, the gate conductor being patterned to be narrower than a spacing to be provided between source and drain electrode contacts to the silicon layer;    laser annealing areas of the amorphous silicon layer not shielded by the gate conductor, through all of the gate insulator layers, to form polycrystalline silicon portions, 
 wherein the gate insulator layers are formed as a gate insulator layer of first refractive index, and an overlying surface insulator layer of second, lower, refractive index.  
   
     
     
         2 . A method as claimed in  claim 1 , wherein the gate insulator layer is at least five times thicker than the surface insulator layer.  
     
     
         3 . A method as claimed in  claim 1  or  2 , wherein a source and drain electrode pattern is provided on the substrate before the formation of the amorphous silicon layer.  
     
     
         4 . A method as claimed in  claim 3 , wherein the face of the substrate on which the source and drain electrode pattern is formed is subjected to plasma treatment to form a doped surface layer having impurity atoms diffused therein, and wherein the laser annealing forms polycrystalline silicon portions having the impurities diffused therein.  
     
     
         5 . A method as claimed in  claim 1  or  2 , wherein a source and drain electrode pattern is formed over the gate insulator, the source and drain electrodes contacting the silicon layer though wells defined in the gate insulator.  
     
     
         6 . A method as claimed in any preceding claim, wherein the gate insulator comprises first and second gate insulator layers, the first gate insulator layer being patterned with the amorphous silicon layer to define a semiconductor island of the transistor with an overlying first gate insulator layer.  
     
     
         7 . A method as claimed in any preceding claim, wherein the gate insulator layer comprises silicon nitride, and the surface insulator comprises silicon oxide.  
     
     
         8 . A method as claimed in any preceding claim, wherein the laser annealing process comprises exposing the structure to laser light of predetermined wavelength, the thickness of the surface insulator being selected depending on the wavelength, to reduce the effect of thickness variations in the gate insulator layer and/or the surface insulator on the reflectance of the structure at the predetermined wavelength.  
     
     
         9 . A method of producing a top gate thin-film transistor, comprising the steps of: 
 forming an amorphous silicon layer over an insulating substrate;    treating the silicon layer to form a polysilicon layer;    forming an insulated gate structure over the amorphous silicon layer comprising gate insulator layers and an upper gate conductor directly over the gate insulator layers, the gate conductor being patterned to be narrower than a spacing to be provided between source and drain electrode contacts to the silicon layer;    implanting a dopant into the regions of the polysilicon layer not shielded by the gate conductor;    laser treating the regions of the polysilicon layer not shielded by the gate conductor to activate the dopant atoms, 
 wherein the gate insulator layers are formed as a gate insulator layer of first refractive index, and an overlying insulator layer of second, lower, refractive index.  
   
     
     
         10 . A method as claimed in  claim 9 , wherein the gate insulator layers are formed as a lower gate insulator layer, the gate insulator layer of first refractive index overlying the lower gate insulator and the overlying insulator layer of second, lower, refractive index.  
     
     
         11 . A method as claimed in  claim 10 , wherein the lower gate insulator comprises an oxide, the gate insulator layer of first refractive index comprises a nitride and the gate insulator of second, lower, refractive index comprises an oxide.  
     
     
         12 . A method as claimed in  claim 11 , wherein the lower gate insulator comprises silicon oxide, the gate insulator layer of first refractive index comprises silicon nitride and the gate insulator of second, lower, refractive index comprises silicon oxide.  
     
     
         13 . A method as claimed in  claim 12 , wherein each silicon oxide layer has a thickness of 8 to 15 nm and the silicon nitride layer has a thickness of between 15 and 30 nm.  
     
     
         14 . A method as claimed in any one of  claims 9  to  13 , wherein a source and drain electrode pattern is formed over the gate insulator, the source and drain electrodes contacting the silicon layer though wells defined in the gate insulator.  
     
     
         15 . A method as claimed in any one of  claims 9  to  14 , wherein the laser annealing process comprises exposing the structure to laser light of predetermined wavelength, the thickness of the gate insulator layers being selected depending on the wavelength, to reduce the effect of thickness variations in the gate insulator layers on the reflectance of the structure at the predetermined wavelength.  
     
     
         16 . A top gate thin-film transistor comprising: 
 a silicon layer provided over an insulating substrate;    an insulated gate structure over the silicon layer, comprising a gate insulator and an upper gate conductor, the gate conductor being patterned to be narrower than a spacing between source and drain electrode contacts to the silicon layer, the silicon layer in the region of the source and drain electrodes comprising polycrystalline silicon, 
 wherein the gate insulator comprises a gate insulator layer of first refractive index, and an overlying upper gate insulator layer of second, lower, refractive index, the gate conductor being provided over the upper gate insulator layer, the gate insulator layer and the upper gate insulator layer extending fully across the spacing between contacts of the source and drain to the silicon layer.  
   
     
     
         17 . A transistor as claimed in  claim 16 , wherein the silicon layer beneath the gate conductor comprises amorphous silicon.  
     
     
         18 . A transistor as claimed in  claim 16 , wherein the silicon layer beneath the gate conductor comprises polycrystalline silicon.  
     
     
         19 . A transistor as claimed in  claim 16 ,  17  or  18  wherein the silicon layer in the region of the source and drain electrodes comprises doped polycrystalline silicon.  
     
     
         20 . A transistor as claimed in any one of  claims 16  to  19 , wherein the gate insulator comprises first and second gate insulator layers, the first gate insulator layer corresponding in pattern to the silicon layer.  
     
     
         21 . A transistor as claimed in any one of  claims 16  to  20 , wherein the gate insulator layer comprises silicon nitride, and the upper gate insulator layer comprises silicon oxide.  
     
     
         22 . A transistor as claimed in any one of  claims 16  to  21 , wherein the gate insulator comprises a lower gate insulator layer, the gate insulator layer of first refractive index overlying the lower gate insulator and the upper gate insulator layer.  
     
     
         23 . A transistor as claimed in  claim 22 , wherein the lower gate insulator layer comprises an oxide, the gate insulator layer of first refractive index comprises a nitride and the upper gate insulator layer comprises an oxide.  
     
     
         24 . A transistor as claimed in  claim 23 , wherein the lower gate insulator layer comprises silicon oxide, the gate insulator layer of first refractive index comprises silicon nitride and the upper gate insulator comprises silicon oxide.  
     
     
         25 . A transistor as claimed in  claim 24 , wherein each silicon oxide layer has a thickness of 8 to 15 nm and the silicon nitride layer has a thickness of between 15 and 30 nm.