Low-temperature polysilicon thin film transistor having buried LDD structure and process for producing same

Abstract

A low-temperature polysilicon thin film transistor having a buried LDD structure is provided. Two heavily doped regions are formed in a semiconductor layer and distributed just below a surface of the semiconductor layer. Two LDD regions are both sandwiched between the two heavily doped regions in a direction substantially parallel to the surface of semiconductor layer, and separated from the surface of the semiconductor layer by a portion of the semiconductor layer. The process for producing such a thin film transistor is also provided. A first, a second and a third doping materials are injected into a semiconductor layer in different directions to form heavily doped regions and LDD regions.

What is claimed is:  
     
         1 . A thin film transistor, comprising: 
 a semiconductor layer;    an insulator layer on said semiconductor layer;    a first heavily doped region and a second heavily doped region in said semiconductor layer and distributed just below a surface of said semiconductor layer;    a first LDD region and a second LDD region, both sandwiched between said first heavily doped region and said second heavily doped region in a first direction, and between two portions of said semiconductor layer in a second direction substantially perpendicularly to said first direction, said first LDD region and said second LDD region being immediately adjacent to said first heavily doped region and said second heavily doped region, respectively, and having therebetween a channel region in said first direction; and    a gate electrode formed on said insulator layer and over said channel region.    
     
     
         2 . The thin film transistor according to  claim 1  wherein said first direction is substantially parallel to said surface of said semiconductor, and said second direction is substantially normal to said surface of said semiconductor.  
     
     
         3 . The thin film transistor according to  claim 1  further comprising: 
 a dielectric layer on said gate electrode and said insulator layer; and  
 a source conductive line and a drain conductive line penetrating through said insulator layer and said dielectric layer to contact with said first heavily doped region and said second heavily doped region, respectively.  
 
     
     
         4 . The thin film transistor according to  claim 1  wherein said semiconductor layer is made of polycrystalline silicon.  
     
     
         5 . The thin film transistor according to  claim 1  wherein each of said first heavily doped region and said second heavily doped region is of an N type.  
     
     
         6 . The thin film transistor according to  claim 1  wherein each of said first LDD region and said second LDD region contains a doping material selected from a group consisting of P ions, As ions, PHx ions and AsHx ions.  
     
     
         7 . The thin film transistor according to  claim 1  wherein each of said first LDD region and said second LDD region has more than one doping material selected from a group consisting of P ions, As ions, PHx ions and AsHx ions, and has gradual dopant distributions.  
     
     
         8 . The thin film transistor according to  claim 1  wherein said semiconductor layer is disposed on a glass substrate.  
     
     
         9 . A process for producing a thin film transistor having a buried LDD structure, comprising: 
 providing a semiconductor layer;    forming an insulator layer on said semiconductor layer;    forming a gate electrode on said insulator layer;    injecting a first doping material into said semiconductor layer in a first direction normal to said surface of said semiconductor layer to form a first doped region;    injecting a second doping material into said semiconductor layer in a second direction deviating from said first direction by a first angle to form a second doped region; and    injecting a third doping material into said semiconductor layer in a third direction deviating from said first direction by a second angle to form a third doped region,    wherein said second and said third doped regions partially overlap said first doped region, respectively.    
     
     
         10 . The process according to  claim 9  further comprising a step of forming sidewalls beside said gate electrode.  
     
     
         11 . The process according to  claim 9  wherein the injection step of said first doping material is performed after the forming step of said sidewalls.  
     
     
         12 . The process according to  claim 9  wherein the injection step of said first doping material is performed after the forming step of said gate electrode.  
     
     
         13 . The process according to  claim 9  wherein each of the injection steps of said first, second and third doping material is implemented by one of an ion implantation procedure and an ion shower procedure.  
     
     
         14 . The process according to  claim 9  wherein each of said first, second and third doping material is ions elected from a group consisting of P ions, As ions, PHx ions and AsHx ions.  
     
     
         15 . The process according to  claim 9  wherein each of said second doping material and said third doping material comprises at least two kinds of ions selected from a group consisting of P ions, As ions, PHx ions and AsHx ions.  
     
     
         16 . The process according to  claim 9  wherein said second direction and said third direction are substantially symmetric with respect of said first direction.  
     
     
         17 . The process according to  claim 9  wherein each of said first angle and said second angle is greater than 0° and no greater than 30°.  
     
     
         18 . A process for forming a buried LDD structure of a thin film transistor, comprising: 
 providing a semiconductor layer;    providing a doping mask on said semiconductor layer;    injecting a first doping material into said semiconductor layer in a first direction normal to a surface of said semiconductor layer to form a first doped region;    injecting a second doping material into said semiconductor layer in a second direction having a first incline angle with respect to said first direction to form a second doped region partially overlapping said first doped region; and    injecting a third doping material into said semiconductor layer in a third direction having a second incline angle with respect to said first direction to form a third doped region partially overlapping said first doped region.    
     
     
         19 . The process according to  claim 18  wherein said doping mask is made of a material of a photoresist, and said process further comprises steps of: 
 removing said doping mask;  
 forming an insulator layer on said surface of said semiconductor layer; and  
 forming a gate electrode on said insulator layer at a position corresponding to said doping mask.  
 
     
     
         20 . The process according to  claim 19  wherein the injection step of said first doping material is performed before the removing step of said doping mask, and said injection step of said second doping material is performed after the forming step of said gate electrode.  
     
     
         21 . The process according to  claim 18  wherein said doping mask is a gate electrode of said thin film transistor.  
     
     
         22 . The process according to  claim 18  wherein said first doping material is injected into said semiconductor layer with energy of about 10 keV and dose of about e 15  cm −2 , and said second and third doping materials are injected into said semiconductor layer with energy of about 50˜110 keV and dose of about 5×e 12 ˜1×e 14  cm −2 .