Three dimensional graphic processor

Abstract

A multimedia processor for performing three dimensional graphics processing in an integrated circuit comprises a microprocessor circuit which is configured to generate triangle set-up information corresponding to a plurality of triangles that define a three-dimensional object displayed on a screen. The screen is defined by a plurality of bins having a predetermined number of pixels. A data cache is coupled to the microprocessor and configured to store the set-up information. A three-dimensional triangle rasterizer is coupled to the data cache and configured to perform bin allocation to the triangles so as to identify all bins that intersect with a triangle on the screen.

We claim:  
     
         1 . In an integrated circuit, a multimedia processor for performing three dimensional graphics processing comprising: 
 a microprocessor circuit configured to generate triangle set-up information corresponding to a plurality of triangles that define a three dimensional object displayed on a screen, wherein said screen is defined by a plurality of bins having a predetermined number of pixels;    a data cache coupled to said microprocessor configured to store said set-up information; and    a three dimensional triangle rasterizer coupled to said data cache and configured to perform bin allocation to said triangles so as to identify all bins that intersect with a triangle on said screen.    
     
     
         2 . The multimedia processor in accordance with  claim 1 , wherein said data cache includes a tile index buffer, that stores information relating to each one of said bins.  
     
     
         3 . The multimedia processor in accordance with  claim 2 , wherein said three dimensional triangle rasterizer includes a binning unit that provides tile data information to a local memory unit.  
     
     
         4 . The multimedia processor in accordance with  claim 3 , wherein said three dimensional triangle rasterizer includes a screen coordinate interpolator, that provides the coordinates of intersecting pixels along the sides of each triangle that cross a span line as defined by said binning unit.  
     
     
         5 . The multimedia processor in accordance with claim wherein said binning unit provides a tile data information corresponding to the identification of each triangle in a bin.  
     
     
         6 . The multimedia processor in accordance with  claim 5 , wherein said binning unit divides each one of said triangles into an upper and a lower sub triangles along a horizontal line crossing the middle vertex of each one of said triangles.  
     
     
         7 . The multimedia processor in accordance with  claim 6 , wherein said binning unit identifies said bins in which each one of said upper triangles is located by employing the condition 
         X =[min 2(Cross XAC , Cross XAC+dxdy AC ), max 2(Cross XAB , Cross  XAB+dxdyAB )] 
       wherein, Cross XAC is the x coordinate of the cross point between the edge AC of a triangle ABC, and the next span, and, Cross XAB is the x coordinate of the cross point between the edge AB and the next span.  
     
     
         8 . The multimedia processor in accordance with  claim 6 , wherein said binning unit identifies said bins in which each one of said lower triangles is located by employing the condition 
         X =[min 2(Cross  XAC , Cross  XAC+dxdyAC ), max 3(Cross  XAB, Bx , Cross  XBC )], 
       wherein Cross XAC is the x coordinate of the cross point between the edge AC of a triangle ABC, and the next span, CrossXBC is the x coordinate of the cross point between BC and the next span.  
     
     
         9 . The multimedia processor in accordance with  claim 3 , further comprising a memory unit coupled to said data cache configured to store said tile index information.  
     
     
         10 . The multimedia processor in accordance with  claim 9 , further comprising a data streamer coupled to said memory unit and said data cache configured to transfer data.  
     
     
         11 . In a multimedia processor, a method for performing three dimensional graphics comprising the steps of: 
 generating triangle set-up information corresponding to a plurality of triangles that define a three dimensional object displayed on a screen, wherein said screen is defined by a plurality of bins having a predetermined number of pixels;    storing in a data cache said set-up information; and    for each one of said bins identifying the triangles that intersect said bin.    
     
     
         12 . The method in accordance with  claim 11  further comprising the step of storing in said data cache information relating to each one of said bins.  
     
     
         13 . The method in accordance with  claim 12  further comprising the step of providing tile data information to a memory unit coupled to said data cache.  
     
     
         14 . The method in accordance with  claim 13 , further comprising the step of interpolating screen coordinates so as to provide the coordinates of intersecting pixels along the sides of each triangle that cross a span line as defined by said binning unit.  
     
     
         15 . The method in accordance with  claim 14  further comprising the step of providing a tile data information corresponding to the identification of each triangle in a bin.  
     
     
         16 . The method in accordance with  claim 15  further comprising the step of dividing each one of said triangles into an upper and a lower sub triangles along a horizontal line crossing the middle vertex of each one of said triangles.  
     
     
         17 . The method in accordance with  claim 16  further comprising the step of identifying said bins in which each one of said upper triangles is located.  
     
     
         18 . The method in accordance with  claim 16 , further comprising the step of identifying said bins in which each one of said lower triangles is located.  
     
     
         19 . In an integrated circuit, a multimedia processor for performing three dimensional graphics processing comprising: 
 a microprocessor circuit configured to generate triangle set-up information corresponding to a plurality of triangles that define a three dimensional object displayed on a screen, wherein said screen is defined by a plurality of bins having a predetermined number of pixels;    a data cache coupled to said microprocessor configured to store said set-up information; and    a three dimensional triangle rasterizer coupled to said data cache and configured to perform graphic rasterization so as to provide pixel information for all pixels within each triangle to said data cache.    
     
     
         20 . The multimedia processor in accordance with  claim 19 , wherein said three dimensional triangle rasterizer comprises: 
 a texture coordinate interpolator coupled to said data cache and configured to receive triangle set up information corresponding to each one of said triangles;    a shading color interpolator coupled to said data cache and configured to receive said triangle set-up information corresponding to each one of said triangles; and    a depth interpolator coupled to said data cache and configured to receive said triangle set-up information corresponding to each one of said triangles.    
     
     
         21 . The multimedia processor in accordance with  claim 20 , wherein said texture coordinate interpolator provides texture coordinates of each pixel within said triangles to said data cache.  
     
     
         22 . The multimedia processor in accordance with  claim 20 , wherein said texture coordinate interpolator provides texture coordinates of each pixel that will be visible on said screen to said data cache.  
     
     
         23 . The multimedia processor in accordance with  claim 22  further comprising a three dimensional texture controller coupled to said data cache and configured to generate the memory location of said pixels that will be visible on said screen.  
     
     
         24 . The multimedia processor in accordance with  claim 20  wherein said shading color interpolator provides shading color coordinates of each pixel within said triangles to said data cache.  
     
     
         25 . The multimedia processor in accordance with  claim 20  wherein said shading color interpolator provides shading color coordinates of each pixel that will be visible on said screen to said data cache.  
     
     
         26 . The multimedia processor in accordance with  claim 25  further comprising a three dimensional texture controller coupled to said data cache and configured to generate the memory location of said pixels that will be visible on said screen.  
     
     
         27 . In an integrated circuit, a multimedia processor for performing three dimensional graphics processing comprising: 
 a microprocessor circuit configured to generate triangle set-up information corresponding to a plurality of triangles that define a three dimensional object displayed on a screen, wherein said screen is defined by a plurality of bins having a predetermined number of pixels;    a data cache coupled to said microprocessor configured to store said set-up information;    a three dimensional triangle rasterizer coupled to said data cache and configured to perform graphic rasterization so as to provide pixel information for all pixels within each triangle to said data cache;    a three dimensional texture filter coupled to said data cache and configured to perform filtering of texels received in response to said pixel information provided by said triangle rasterizer; and    a video scaler coupled to said texture filter and configured to perform scaling operation for providing a scaled image to a display screen.    
     
     
         28 . The multimedia processor in accordance with  claim 27  wherein said video scaler comprises a multiply and add unit configured to multiply information corresponding to a plurality of neighboring vertical and horizontal pixels with a predetermined coefficient associated with each pixel.  
     
     
         29 . The multimedia processor in accordance with  claim 28  wherein said texture filter includes a horizontal and a linear interpolator coupled to said data cache, and configured to interpolate a plurality of horizontal and vertical texels.  
     
     
         30 . The multimedia processor in accordance with  claim 29 , wherein said linear interpolators receive their interpolation results from said multiply and add unit of said video scaler.