Cyclic redundancy check circuit for use with self-synchronous scramblers

Abstract

The present invention provides a circuit for detecting and correcting errors in a bit stream. The circuit consist of a plurality of circuit elements, an least operation circuit means, and at least two logic gates. The logic gates receive inputs from the plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. The operation circuit elements perform bitwise operations on the contents of at least two of the circuit elements. The bitwise operations are dictated by a CRC polynomial and are used to perform the CRC error detection division operation. At the end of the division process for the data to be checked, each circuit element corresponds to a bit in a bit error pattern, the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bits errors which may be caused by error duplication characteristic of a scrambler.

What is claimed is:  
     
         1 . A circuit for detecting and correcting errors in a bit stream, the circuit including at least two logical gates that determine if at least one of a plurality of conditions is present, each one of said plurality of conditions indicating at least one error in said bit stream and activation of at least one of the at least two logical gates changes a state of a specific bit in said bit stream.  
     
     
         2 . A circuit as defined in  claim 1 , wherein each one of said plurality of conditions is a specific bit pattern denoting a unique error pattern in said bit stream, each bit in said specific bit pattern resulting from bitwise operations between specific selected bits in said bit stream.  
     
     
         3 . A circuit as defined in  claim 2  wherein said plurality of conditions are divided into two groups, a first group which indicates a first type or error in the bit stream and a second group which indicates a second type of error in the bit stream.  
     
     
         4 . A circuit as defined in  claim 3 , wherein if a condition from said first group is detected, the state of a specific bit in said bit stream is changed.  
     
     
         5 . A circuit as defined in  claim 3 , wherein if a condition from said second group is detected, the state of at least two specific bits in said bit stream is changed.  
     
     
         6 . A circuit as defined in  claim 3 , wherein said first group includes a specific bit error pattern from a group consisting of: 
 Syndrome A.    
     
     
         7 . A circuit as defined in  claim 3 , wherein said second group includes a specific bit error pattern chosen from a group consisting of: 
 Syndrome B.    
     
     
         8 . A circuit as defined in  claim 3 , wherein the at least two logical gates include a first AND gate associated with said first group and a second AND gate associated with said second group, such that said first AND gate is activated if a bit error pattern from said first group is detected and said second AND gate is activated if a bit pattern from said second group is detected.  
     
     
         9 . A circuit as defined in  claim 8 , wherein said first AND gate receives first AND inputs from bits resulting from bitwise operations dictated by the CRC polynomial between specific selected bits in said bit pattern, such that said first AND gate has a predetermined output when said first AND inputs correspond to a bit pattern chosen from a group consisting of: 
 Syndrome A.    
     
     
         10 . A circuit as defined in  claim 9 , wherein the predetermined output is a binary.  
     
     
         11 . A circuit as defined in  claim 9 , wherein the predetermined output is a binary.  
     
     
         12 . A circuit as defined in  claim 8 , wherein said second AND gate receives second AND inputs from bits resulting from bitwise operations dictated by the CRC polynomial between specific selected bits in said bit pattern, such that said second AND gate has a predetermined output when said second AND inputs correspond to a bit pattern chosen from a group consisting of: 
 Syndrome B.    
     
     
         13 . A circuit as defined in  claim 12 , wherein the predetermined output is a binary.  
     
     
         14 . A circuit as defined in  claim 12 , wherein the predetermined output is a binary.  
     
     
         15 . A circuit as defined in  claim 8 , wherein the at least two logical gates includes an OR gate receiving an input from said first AND gate and said second AND gate such that a state of a specific bit in said bit pattern is changed if either said first AND gate or said second AND gate is activated.  
     
     
         16 . A circuit for detecting and correcting errors in a bit stream, said circuit comprising: 
 a plurality of bit circuit elements coupled to receive and store said bit stream, each bit circuit element corresponding to a specific bit in a bit pattern;    at least one operation circuit element for performing operations between the contents of at least two of said bit circuit elements; and    at least two logic gates for determining if the contents of said bit circuit elements match specific bit patterns, at least one of said at least two logic gate receiving inputs from said bit circuit elements;    wherein an output of said circuit causes a state of at least one bit in said bit stream to change if contents of said bit circuit elements match at least one of said plurality of specific bit patterns; and    wherein said bit patterns correspond to errors that have occurred in the transmitted data.    
     
     
         17 . A circuit as defined in  claim 16 , wherein said plurality of specific bit patterns comprises: 
 Syndrome A; and Syndrome B.    
     
     
         18 . A circuit as defined in  claim 16 , wherein said plurality of bit circuit elements are cascaded such that each bit circuit element receives an input from a source chosen from a group consisting of: 
 an immediately preceding bit circuit element;    an output of an which performs a bitwise operation on contents of at least two of said bit circuit elements; and    said bit stream.    
     
     
         19 . A circuit for detecting errors in a bit stream, the circuit comprising: 
 operation means for performing bitwise operations between at least a portion of said bit stream and a bit pattern derived from said bit stream; and    detection means for detecting if a bitwise operation between at least a portion of said bit stream and said bit pattern derived from said bit stream produces a result indicating at least one error in said bit stream;    wherein said operation means implements a bitwise operation corresponding to      B ( x )= Rem ( D ( x )/ G ( x )    where    D(x) is said at least a first portion of said bit stream;    G(x) is said bit pattern derived from said bit stream; and    B(x) is a remainder of a division operation between D(x) and G(x);    such that said detection means detects when B(x) does not equal 0.