Method for filling a wafer through-via with a conductive material

Abstract

A method for filling a via formed through a silicon wafer is disclosed. The method entails mounting the silicon wafer on a mounting substrate and depositing either molten or solid balls of a conductive material into the via. The deposited conductive material may be reflowed to provide electrical contact with other components on the surface of wafer.

What is claimed is:  
     
         1 . A process for filling a with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface, with at least one via extending therethrough from the first surface to the second surface;    mounting the silicon wafer to a mounting substrate;    positioning a device for depositing balls of molten material in line with the via; and    extruding a liquid conductive material through the device for depositing balls of molten material such that the conductive material fills the via to form a conductive via.    
     
     
         2 . The process for filling a via of  claim 1  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         3 . The process for filling a via of  claim 1 , wherein the via has a diameter of at least about 10 micrometers.  
     
     
         4 . The process for filling a via of  claim 1 , wherein the via has a diameter up to about 15 mil.  
     
     
         5 . The process for filling a via of  claim 1 , wherein the via has a diameter up to about 6 mil.  
     
     
         6 . The process for filling a via of  claim 1 , wherein the device for depositing balls of molten material comprises a piezoelectric pressure inducer.  
     
     
         7 . The process for filling a via of  claim 1 , wherein the conductive material comprises solder or a conductive polymer.  
     
     
         8 . The process for filling a via of  claim 1 , wherein the solder is an alloy selected from the group consisting of about 95% Pb/5% Sn, about 60% Pb/40% Sn, about 63% In/37% Sn and about 62% Pb/36% Sn/2% Ag.  
     
     
         9 . The process for filling a via of  claim 1 , further comprising, after the step of extruding the conductive material, the step of: 
 reflowing the conductive material to fill the via.    
     
     
         10 . A process for filling a via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer with at least one through-via;    mounting the silicon wafer onto a surface of a mounting substrate, the mounting substrate surface having at least one cavity, wherein the silicon wafer is positioned such that the through-via is located in line with the cavity;    positioning a solder jet nozzle in line with the through-via; and    extruding a liquid conductive material through the solder jet nozzle such that the conductive material fills the through-via and the cavity in the mounting substrate to form a conductive via.    
     
     
         11 . The process for filling a through-via of  claim 10  wherein the silicon wafer has a thickness of at least about 28 mil.  
     
     
         12 . The process for filling a through-via of  claim 10  wherein the solder jet nozzle comprises a piezoelectric pressure inducer.  
     
     
         13 . The process for filling a through-via of  claim 10  further comprising the step of: 
 reflowing the conductive material to fill the via.  
 
     
     
         14 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer with at least one through-via;    mounting the silicon wafer onto a surface of a mounting substrate, the mounting substrate comprising a circuit substrate having at least one interconnect, wherein the silicon wafer is positioned such that the through-via is located in line with the interconnect;    positioning a device for depositing balls of molten material in line with the through-via; and    extruding a liquid conductive material through the device for depositing balls of molten material such that the conductive material fills the through-via in electrical contact with the interconnect.    
     
     
         15 . The process for filling a through-via of  claim 14  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         16 . The process for filling a through-via of  claim 14  wherein the solder jet nozzle comprises a piezoelectric pressure inducer.  
     
     
         17 . The process for filling a via of  claim 14 , further comprising, after the step of extruding the conductive material, the step of: 
 reflowing the conductive material to fill the via.    
     
     
         18 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface, the first surface comprising at least one first interconnect with at least one via;    mounting the silicon wafer onto a surface of a mounting substrate, such that the second surface of the wafer is in contact with the mounting substrate;    positioning a device for depositing balls of molten material in line with the through-via;    extruding a liquid conductive material through the device for depositing balls of molten material such that the conductive material fills the through-via to form a conductive via in electrical contact with the first interconnect.    
     
     
         19 . The process for filling a through-via of  claim 18  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         20 . The process for filling a through-via of  claim 18  wherein the solder jet nozzle comprises a piezoelectric pressure inducer.  
     
     
         21 . The process for filling a via of  claim 18 , further comprising, after the step of extruding the conductive material, the step of: 
 reflowing the conductive material to fill the via.    
     
     
         22 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface generally opposed to each other with at least one through-via, wherein the first surface comprises an electrical interconnect;    mounting the silicon wafer onto a surface of a mounting substrate such that the second surface of the silicon wafer is in contact with the surface of the mounting substrate, the mounting substrate surface having at least one cavity, wherein the silicon wafer is positioned such that the through-via is located in line with the cavity;    positioning a device for depositing balls of molten material in line with the through-via; and    extruding a liquid conductive material through the solder jet nozzle such that the conductive material fills both the through-via and the cavity in the mounting substrate and the conductive material wets the interconnect to form a conductive via.    
     
     
         23 . The process for filling a through-via of  claim 22  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         24 . The process for filling a through-via of  claim 22  wherein the solder jet nozzle comprises a piezoelectric pressure inducer.  
     
     
         25 . The process for filling a via of  claim 22 , further comprising, after the step of extruding the conductive material, the step of: 
 reflowing the conductive material to fill the via.    
     
     
         26 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface generally opposed to each other, the first surface comprising at least one first interconnect with at least one through-via extending therethrough from the first surface to the second surface;    mounting the silicon wafer onto a surface of a mounting substrate, such that the second surface of the wafer is in contact, the mounting substrate comprising a circuit substrate the mounting substrate surface having at least one second interconnect, wherein the silicon wafer is positioned such that the through-via is located in line with the second interconnect;    positioning a device for depositing balls of molten material in line with the through-via;    extruding a liquid conductive material through the device for depositing balls of molten material such that the conductive material fills the via to form a conductive via in electrical contact with the first interconnect and the second interconnect.    
     
     
         27 . The process for filling a through-via of  claim 26  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         28 . The process for filling a through-via of  claim 26  wherein the solder jet nozzle comprises a piezoelectric pressure inducer.  
     
     
         29 . The process for filling a via of  claim 26 , further comprising, after the step of extruding the conductive material, the step of: 
 reflowing the conductive material to fill the via.    
     
     
         30 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface, with at least one via extending therethrough from the first surface to the second surface;    mounting the silicon wafer to a mounting substrate;    providing a multiplicity of conductive material balls one or more discrete portions of a conductive material;    depositing conductive material balls in the through-via by means of a vacuum nozzle or tube, such that sufficient conductive material is deposited in the via to fill the via; and    reflowing the conductive material in the through-via to form a conductive via.    
     
     
         31 . The process for filling a through-via of  claim 30  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         32 . The process for filling a through-via of  claim 30  wherein the through-via has a diameter of at least about 10 micrometers.  
     
     
         33 . The process for filling a through-via of  claim 30  wherein the via has a diameter up to about 15 mil.  
     
     
         34 . The process for filling a through-via of  claim 31  wherein the via has a size up to about 6 mil.  
     
     
         35 . The process for filling a through-via of  claim 30  wherein the conductive material comprises solder or a conductive polymer.  
     
     
         36 . The process for filling a through-via of  claim 30  wherein the solder is an alloy selected from the group consisting of about 95% Pb/5% Sn, about 60% Pb/40% Sn, about 63% In/37% Sn and about 62% Pb/36% Sn/2% Ag.  
     
     
         37 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer with at least one through-via;    mounting the silicon wafer onto a surface of a mounting substrate, the mounting substrate surface having at least one cavity, wherein the silicon wafer is positioned such that the through-via is located in line with the cavity;    said cavity optionally may be presented partially filled with conductive material;    providing a multiplicity of conductive material balls;    depositing conductive material balls in the through-via by means of a vacuum nozzle or tube, such that sufficient conductive material is deposited in the via to fill the via; and    reflowing the conductive material in the through-via to form a conductive via.    
     
     
         38 . The process for filling a through-via of  claim 37  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         39 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface generally opposed to each other, the first surface comprising at least one first interconnect with at least one through-via;    mounting the silicon wafer onto a surface of a mounting substrate, such that the second surface of the wafer is in contact with the surface of the mounting substrate, the mounting substrate comprising a circuit substrate the mounting substrate surface having at least one second interconnect, wherein the silicon wafer is positioned such that the through-via is located in line with the second interconnect;    providing a multiplicity of conductive material balls;    depositing conductive material balls in the through-via by means of a vacuum nozzle or tube, such that sufficient conductive material is deposited in the via to fill the via; and    reflowing the conductive material in the through-via such that the conductive material fills the through-via to form a conductive via in electrical contact with the first interconnect and the second interconnect.    
     
     
         40 . The process for filling a through-via of  claim 39  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         41 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer with at least one through-via;    mounting the silicon wafer onto a surface of a mounting substrate, the mounting substrate surface having at least one cavity, wherein the silicon wafer is positioned such that the through-via is located in line with the cavity;    providing a multiplicity of conductive material balls;    depositing conductive material balls in the through-via by means of a vacuum nozzle or tube, such that sufficient conductive material is deposited in the via to fill the via; and    reflowing the conductive material in the through-via such that the conductive material fills the through-via and the cavity in the mounting substrate to form a conductive via.    
     
     
         42 . The process for filling a through-via of  claim 41  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         43 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface generally opposed to each other with at least one through-via, wherein the first surface comprises an electrical interconnect;    mounting the silicon wafer onto a surface of a mounting substrate such that the second surface of the silicon wafer is in contact with the surface of the mounting substrate, the mounting substrate surface having at least one cavity, wherein the silicon wafer is positioned such that the through-via is located in line with the cavity;    providing a multiplicity of conductive material balls;    depositing conductive material balls in the through-via by means of a vacuum nozzle or tube, such that sufficient conductive material is deposited in the via to fill the via; and    reflowing the conductive material in the through-via such that the conductive material fills both the through-via and the cavity in the mounting substrate and the conductive material wets the interconnect to form a conductive via.    
     
     
         44 . The process for filling a through-via of  claim 43  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         45 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer with at least one through-via;    mounting the silicon wafer onto a surface of a mounting substrate the mounting substrate comprising a circuit substrate, the mounting substrate surface having at least one interconnect, wherein the silicon wafer is positioned such that the through-via is located in line with the interconnect;    providing a multiplicity of conductive material balls;    depositing conductive material balls in the through-via by means of a vacuum nozzle or tube, such that sufficient conductive material is deposited in the via to fill the via; and    reflowing the conductive material in the through-via such that the conductive material fills the through-via in electrical contact with the interconnect.    
     
     
         46 . The process for filling a through-via of  claim 45  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         47 . A process for filling a through-via with a conductive material, the process comprising the steps of: 
 providing a silicon wafer having a first surface and a second surface generally opposed to each other, the first surface comprising at least one first interconnect with at least one through-via;    mounting the silicon wafer onto a surface of a mounting substrate, such that the second surface of the wafer is in contact, the mounting substrate comprising a circuit substrate the mounting substrate surface having at least one second interconnect, wherein the silicon wafer is positioned such that the through-via is located in line with the second interconnect;    providing a multiplicity of conductive material balls;    depositing conductive material balls in the through-via by means of a vacuum nozzle or tube, such that sufficient conductive material is deposited in the via to fill the via; and    reflowing the conductive material in the through-via such that the conductive material fills the through-via to form a conductive via in electrical contact with the first interconnect and the second interconnect.    
     
     
         48 . The process for filling a through-via of  claim 47  wherein the silicon wafer has a thickness of at least about 6 mil.  
     
     
         49 . An assembly for testing silicon wafers comprising: 
 a silicon wafer comprising a first surface and a second surface generally opposed to each other the first surface comprising at least one interconnect the wafer having at least one through-via extending from the first surface to the second surface, the through-via being completely filled with a conductive material, wherein the interconnect is electrically connected to the through-via;    a testing circuit comprising at least one contact pad; wherein the wafer is mounted on the testing circuit such that the second surface of the wafer abuts the surface of the testing circuit having the contact pad wherein the contact pad is an electrical connection with the conductive material of the through-via.    
     
     
         50 . The testing apparatus of  claim 49  wherein the wafer is at least about 6 mil thick.  
     
     
         51 . The assembly of  claim 49  wherein the interconnect and the through-via are electrically connected by means of a metallized trace.  
     
     
         52 . The assembly of  claim 51  wherein the metallized trace is an aluminum or copper trace.  
     
     
         53 . The assembly of  claim 49  wherein the second surface of the wafer further comprises metallized traces or pads that act as capture pads.