Serially sensing the output of multilevel cell arrays

Abstract

In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.

What is claimed is:  
     
         1 . A method comprising: 
 providing the output from an array cell to a first input of a sense amplifier;    feeding back the output of the sense amplifier to a latch; and    feeding the output from the latch to control logic to select one of at least two references based on the output of said sense amplifier.    
     
     
         2 . The method of  claim 1  wherein feeding back the output of the sense amplifier to a latch includes feeding back the output of the sense amplifier to a latch arranged in parallel to the sense amplifier.  
     
     
         3 . The method of  claim 1  wherein feeding back the output of the sense amplifier to a latch includes feeding back the output of the sense amplifier to a latch arranged in series with said sense amplifier.  
     
     
         4 . The method of  claim 1  further including level shifting the output of said latch.  
     
     
         5 . The method of  claim 1  including controlling switchable elements to select one of at least two references to apply to a second input to said sense amplifier.  
     
     
         6 . A multilevel memory comprising: 
 a sense amplifier coupled to an array cell to be sensed; and    a first latch coupled to the output of said sense amplifier, said latch to store a signal to select between one of two reference levels to be coupled to the sense amplifier.    
     
     
         7 . The memory of  claim 6  including a periphery output latch coupled to said sense amplifier, wherein said first latch is parallel to said periphery output latch.  
     
     
         8 . The memory of  claim 7  wherein said first latch is in a feedback loop that feeds back the output of said sense amplifier to select one of at least two reference levels.  
     
     
         9 . The memory of  claim 6  including a periphery output latch, wherein said first latch is between the sense amplifier and the periphery output latch.  
     
     
         10 . The memory of  claim 6  including control logic and level shifting coupled to said latch.  
     
     
         11 . The memory of  claim 6  including a pair of switchable elements each coupled to a different one of at least two reference levels, said switchable elements coupled to be operated by the output of said latch.  
     
     
         12 . The memory of  claim 6  wherein said memory is a flash memory.  
     
     
         13 . The memory of  claim 6  wherein said sense amplifier output is also coupled to a periphery output latch.  
     
     
         14 . The memory of  claim 9  wherein said control logic and level shifting is in parallel with said sense amplifier.  
     
     
         15 . A multilevel cell memory comprising: 
 a sense amplifier having an output;    a first path coupled to the output of said sense amplifier to selectively receive the more significant bit data from the sense amplifier; and    a second path coupled to the output of said sense amplifier to selectively receive less significant bit data from said sense amplifier.    
     
     
         16 . The memory of  claim 15  including a first latch on said first path to store more significant bit data.  
     
     
         17 . The memory of  claim 16  including a second latch on said first path to store more significant bit data.  
     
     
         18 . The memory of  claim 15  including a third latch on said second path to store less significant bit data.  
     
     
         19 . The memory of  claim 15  including a multiplexer to output sensed data including more and less significant bit data.  
     
     
         20 . The memory of  claim 17  wherein said first latch is selectively operable to pass more significant bit data to said second latch.  
     
     
         21 . The memory of  claim 20 , including a multiplexer, wherein said second latch is selectively operable to pass more significant bit data to the multiplexer.  
     
     
         22 . The memory of  claim 18 , including a multiplexer, wherein said third latch on said second path is selectively operable to output less significant bit data to the multiplexer.  
     
     
         23 . The memory of  claim 22  including a switch that selectively couples said first latch to said second latch and said sense amplifier to said third latch.  
     
     
         24 . A method comprising: 
 selectively passing more significant bit data from the output of a multilevel cell sense amplifier to a first latch; and    selectively passing less significant bit data from said sense amplifier to a second latch.    
     
     
         25 . The method of  claim 24  including selectively passing the more significant data from said first latch to a third latch.  
     
     
         26 . The method of  claim 25  including storing data in said sense amplifier, and said first, second and third latches.  
     
     
         27 . The method of  claim 26  including providing a pair of paths, one of said paths including said first and third latches and the other of said paths including said second latch.  
     
     
         28 . The method of  claim 27  including isolating said first path from said second path when said less significant bit data is being output from said sense amplifier.  
     
     
         29 . The method of  claim 28  including selectively opening said first and second paths at the same time.  
     
     
         30 . The method of  claim 27  including selectively opening said first path to isolate said first path from said second path.  
     
     
         31 . The method of  claim 25  including transferring more significant bit data from said first latch after said less significant bit data has been loaded in said second latch.  
     
     
         32 . An article comprising a medium storing instructions that enable a processor-based system to: 
 selectively pass more significant bit data from the output of a multilevel cell sense amplifier to a first latch; and    selectively pass less significant bit data from said sense amplifier to a second latch.    
     
     
         33 . The article of  claim 32  wherein said medium stores instructions that enable a processor-based system to selectively pass the more significant data from said first latch to a third latch.  
     
     
         34 . The article of  claim 33  wherein said medium stores instructions that enable a processor-based system to store data in said sense amplifier, and said first, second and third latches.  
     
     
         35 . The article of  claim 34  wherein said medium stores instructions that enable a processor-based system to select one of a pair of paths, one of said paths including said first and third latches and the other of said paths including said second latch.  
     
     
         36 . The article of  claim 35  wherein said medium stores instructions that enable a processor-based system to isolate said first path from said second path when said less significant bit data is being provided from said sense amplifier.  
     
     
         37 . The article of  claim 36  wherein said medium stores instructions that enable a processor-based system to selectively open said first and second paths at the same time.  
     
     
         38 . The article of  claim 35  wherein said medium stores instructions that enable a processor-based system to selectively open said first path to isolate said first path from said second path.  
     
     
         39 . The article of  claim 33  wherein said medium stores instructions that enable a processor-based system to transfer more significant bit data from said first latch after said less significant bit data has been loaded in said second latch.  
     
     
         40 . A multilevel memory cell comprising: 
 a sense amplifier;    a circuit coupled to the output of said sense amplifier;    a latch coupled to said circuit; and    said circuit including a driver coupled to a pass gate, said driver coupled to an output of said sense amplifier, and said pass gate coupled to said latch.    
     
     
         41 . The memory of  claim 40 , including a first driver and pass gate coupled to a first output of said sense amplifier, and a second driver and pass gate coupled to the second output of said sense amplifier.  
     
     
         42 . The memory of  claim 41  including a pull-up transistor coupled between each driver and pass gate to charge the node between said driver and said pass gate when said pass gates are turned off.  
     
     
         43 . The memory of  claim 42  wherein said pull-up transistor has a gate coupled to an inverter, said inverter coupled to a signal also coupled to the gate of said pass gates.  
     
     
         44 . The memory of  claim 43  wherein said drivers, pass gates, and pull-up transistors are PMOS transistors.  
     
     
         45 . A method comprising: 
 providing an output from an array cell to a first input of a sense amplifier; and    feeding back the output of the sense amplifier to a latch through a driver coupled to a pass gate.    
     
     
         46 . The method of  claim 45  including coupling a first output of the sense amplifier through a first driver and pass gate and coupling a second output of said sense amplifier through a second driver and pass gate to said latch.  
     
     
         47 . The method of  claim 46  including biasing the node between each pass gate and driver.  
     
     
         48 . The method of  claim 47  wherein said nodes are selectively biased when the pass gates are turned off.