Integrated circuit provided with overvoltage protection and method for manufacture thereof

Abstract

The invention concerns an integrated circuit, comprising a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a V cc power supply terminal, an input point (in) and an output point (out). At least one of the V cc power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, wherein the overvoltage protection circuit comprises means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point. The means comprise two or more diode elements of the Zener type connected in series. The substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate. A first diode element is provided in the substrate of the first conductivity type and is formed by a first pn junction between two surface areas (S 1 ,S 2 ) of opposed conductivity types arranged in the substrate. At least one second diode element is provided in the well of the second conductivity type and is formed by a second pn junction between two surface areas (S 3 ,S 4 ) of opposed conductivity types arranged in the well, wherein the well insulates at least the second diode element from the first diode element.

1 . Integrated circuit, comprising a substrate (SBSTR) with sub-circuits provided with a number of terminals, including a substrate terminal or earthing point (GND), a V cc  power supply terminal, an input point (in) and an output point (out), wherein at least one of the V cc  power supply terminal, the input point or the output point is connected via an overvoltage protection circuit to the substrate terminal or earthing point, wherein the overvoltage protection circuit comprises means with diode action formed in the substrate between the relevant terminal and the substrate terminal or earthing point, wherein the means comprise two or more diode elements of the Zener type connected in series, and the substrate of a first conductivity type is provided with a well (WLL) of a second, opposed conductivity type formed in the substrate and wherein a first diode element is provided in the substrate of the first conductivity type and is formed by a first pn junction between two surface areas (S 1 ,S 2 ) of opposed conductivity types arranged in the substrate, and at least one second diode element is provided in the well of the second conductivity type and is formed by a second pn junction between two surface areas (S 3 ,S 4 ) of opposed conductivity types arranged in the well and wherein the well insulates at least the second diode element from the first diode element.  
     
     
         2 . Integrated circuit as claimed in  claim 1 , wherein the anode part (S 1 ) of the first diode element is electrically connected to the substrate terminal or earthing point and the cathode part (S 2 ) is electrically connected to the anode part (S 3 ) of the second diode element, and the cathode part (S 4 ) of the second diode element is electrically connected to the anode part of a further diode element or to the relevant terminal (V cc , in, out).  
     
     
         3 . Integrated circuit as claimed in  claim 1  or  2 , wherein an n +  surface area (S 2 ,S 4 ) of the p-n junction is formed in a p +  surface area (S 1 ,S 3 ).  
     
     
         4 . Integrated circuit as claimed in  claim 3 , wherein the n +  surface area (S 4 ,FIG. 2) of the p-n junction of the second diode element and the well are mutually separated by the p +  surface area (S 3 ).  
     
     
         5 . Integrated circuit as claimed in  claim 4 , comprising a surface area (S 5 ) arranged in the well of conductivity type corresponding with the conductivity type of the well in order to bring the well to appropriate voltage.  
     
     
         6 . Integrated circuit as claimed in  claim 1 , wherein an n +  surface area (S 2 ,S 4 ; FIG. 3) and a p +  surface area (S 1 ,S 3 ) of a diode element are positioned immediately adjacently of each other.  
     
     
         7 . Integrated circuit as claimed in  claim 1 , wherein the p +  surface area (S 1 ,S 3 ; FIG. 4) is formed inside the n +  surface area (S 2 ,S 4 ) and interrupts the interface with the substrate.  
     
     
         8 . Integrated circuit as claimed in any of the claims  3 - 7 , wherein the p +  and n +  surface areas are interchanged.  
     
     
         9 . Integrated circuit as claimed in any of the foregoing claims, wherein a diode element has a Zener voltage of about 5 Volt.  
     
     
         10 . Method for manufacturing a protection circuit as claimed in any of the foregoing claims, comprising of: 
 arranging a well (WLL) of a second conductivity type in a substrate (SBSTR) of a first conductivity type by diffusion;    arranging a highly doped surface area (S 3 ) of the second conductivity type in the well by diffusion;    arranging a highly doped surface area (S 1 ) of the second conductivity type in the substrate by diffusion;    arranging highly doped surface areas (S 2 ,S 4 ) of the first conductivity type in the highly doped surface areas of the second conductivity type by diffusion.    
     
     
         11 . Overvoltage protection circuit, evidently intended for an integrated circuit as claimed in at least one of the claims  1 - 9 .