Thin film memory, array, and operation method and manufacture method therefor

Abstract

A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

What is claimed is:  
     
         1 . A thin film memory cell comprising: 
 a semiconductor thin film having a first principal surface and a second principal surface that faces the first principal surface;    a first gate insulating film formed on the first principal surface of the semiconductor thin film;    a first conductive gate formed on the first gate insulating film;    a first semiconductor region and a second semiconductor region which face each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film, and which have a first conductivity type; and    a third semiconductor region which has the opposite conductivity type and which is in contact with the semiconductor thin film,    wherein a portion of the semiconductor thin film that is sandwiched between the first semiconductor region and the second semiconductor region forms a first channel formation semiconductor thin film portion,    wherein the semiconductor thin film is extended between the first channel formation semiconductor thin film portion and the third semiconductor region of the opposite conductivity type to form a second channel formation semiconductor thin film portion, and    wherein a second gate insulating film is formed on the extended portion of the semiconductor thin film and a second conductive gate is formed on the second gate insulating film.    
     
     
         2 . A thin film memory cell according to  claim 1 , wherein the first conductive gate and the second conductive gate are continuous.  
     
     
         3 . A thin film memory cell according to  claim 1 , wherein the second gate insulating film and the second conductive gate are continuous with the first gate insulating film and the first conductive gate.  
     
     
         4 . A thin film memory cell according to  claim 1 , wherein the extended portion of the semiconductor thin film has a portion whose impurity concentration is different from the impurity concentration of the semiconductor thin film portion that is sandwiched between the first and second semiconductor regions.  
     
     
         5 . A thin film memory cell according to  claim 1 , wherein the extended portion of the semiconductor thin film has an impurity portion whose conductivity type is different from the conductivity type of the semiconductor thin film portion that is sandwiched between the first and second semiconductor regions.  
     
     
         6 . A thin film memory cell comprising: 
 a semiconductor thin film having a first principal surface and a second principal surface that faces the first principal surface;    a first gate insulating film formed on the first principal surface of the semiconductor thin film;    a first conductive gate formed on the first gate insulating film;    a first semiconductor region and a second semiconductor region which face each other across the first conductive gate, which are insulated from the first conductive gate, which are in contact with the semiconductor thin film, and which have a first conductivity type; and    a third semiconductor region which has the opposite conductivity type and which is in contact with the semiconductor thin film in a part of area below the first conductive gate in the direction that crosses substantially at right angels with the direction in which the first semiconductor region and the second semiconductor region face each other,    wherein a portion of the semiconductor thin film that is sandwiched between the first semiconductor region and the second semiconductor region forms a first channel formation semiconductor thin film portion, and    wherein the semiconductor thin film is extended between the first channel formation semiconductor thin film portion and the third semiconductor region of the opposite conductivity type to form a second channel formation semiconductor thin film portion.    
     
     
         7 . A thin film memory cell according to  claim 6 , wherein the second channel formation semiconductor thin film portion has a portion whose impurity concentration is different from the impurity concentration of the first channel formation semiconductor thin film portion.  
     
     
         8 . A thin film memory cell according to  claim 6 , wherein the second channel formation semiconductor thin film portion has an impurity portion whose conductivity type is different from the conductivity type of the first channel formation semiconductor thin film portion.  
     
     
         9 . A thin film memory cell according to  claim 1 , wherein the semiconductor thin film is formed on an insulating substrate.  
     
     
         10 . A thin film memory cell according to  claim 1 , wherein at least the one end of the semiconductor thin film is supported by substrate.  
     
     
         11 . A thin film memory cell according to  claim 1 , further comprising: 
 a third gate insulating film formed on the second principal surface in the portion where the semiconductor thin film is sandwiched between the first semiconductor region and the second semiconductor region; and    a third conductive gate that is in contact with the third gate insulating film.    
     
     
         12 . A thin film memory cell according to  claim 11 , wherein a surface portion of a substrate supporting the semiconductor thin film serves as the third conductive gate.  
     
     
         13 . A thin film memory array comprising: 
 a plurality of word lines;    a plurality of writing bit lines that are insulated from and intersect the word lines;    a plurality of reading bit lines running by the side of the writing bit lines;    a plurality of common lines; and    a plurality of memory cells according to  claim 12 ,    wherein, in a portion where one of the plural word lines, one of the plural writing bit lines, and a reading bit line that runs along the one writing bit line intersect one another, the first and second conductive gates of one of the plural memory cells are connected to the one word line out of the plural word lines,    wherein the first semiconductor region of the one memory cell is connected to the one reading bit line out of the plural reading bit lines,    wherein the second semiconductor region of the one memory cell is connected to one of the plural common lines, and    wherein the third semiconductor region of the one memory cell is connected to the one writing bit line out of the plural writing bit lines.    
     
     
         14 . A thin film memory array comprising: 
 a plurality of word lines;    a plurality of writing bit lines that are insulated from and intersect the word lines;    a plurality of reading bit lines running by the side of the writing bit lines;    a plurality of common lines; and    a plurality of memory cells according to  claim 12 ,    wherein, in a portion where one of the plural word lines, one of the plural writing bit lines, and a reading bit line that runs along the one writing bit line intersect one another, the first conductive gate of one of the plural memory cells is connected to the one word line out of the plural word lines,    wherein the first semiconductor region of the one memory cell is connected to the one reading bit line out of the plural reading bit lines,    wherein the second semiconductor region of the one memory cell is connected to one of the plural common lines, and    wherein the third semiconductor region of the one memory cell is connected to the one writing bit line out of the plural writing bit lines.    
     
     
         15 . A thin film memory array comprising: 
 a plurality of word lines;    a plurality of bit lines that are insulated from and intersect the word lines;    a plurality of common lines; and    a plurality of memory cells according to  claim 12 ,    wherein, in a portion where one of the plural word lines and one of the plural bit lines intersect one another, the first and second conductive gates of one of the plural memory cells are connected to the one word line out of the plural word lines,    wherein the first semiconductor region and the third semiconductor region of the one memory cell is connected to the one bit line out of the plural bit lines, and    wherein the second semiconductor region of the one memory cell is connected to one of the plural common lines.    
     
     
         16 . A thin film memory array comprising: 
 a plurality of word lines;    a plurality of bit lines that are insulated from and intersect the word lines;    a plurality of common lines; and    a plurality of memory cells according to  claim 12 ,    wherein, in a portion where one of the plural word lines and one of the plural bit lines intersect one another, the first conductive gate of one of the plural memory cells is connected to the one word line out of the plural word lines,    wherein the first semiconductor region and the third semiconductor region of the one memory cell is connected to the one bit line out of the plural bit lines, and    wherein the second semiconductor region of the one memory cell is connected to one of the plural common lines.    
     
     
         17 . A thin film memory array according to  claim 15 , 
 wherein the first conductive gate and the second conductive gate are continuous throughout one cell and are continued further to extend between cells adjacent in the word direction to form a part of a word line, and    wherein the first channel formation semiconductor thin film portion or the second channel formation semiconductor thin film portion in one cell is separated from that of its adjacent cell.    
     
     
         18 . A thin film memory array according to  claim 16 , 
 wherein the first conductive gate is extended to be continuous between cells adjacent in the word direction and forms a part of a word line, and    wherein the first channel formation semiconductor thin film portion or the second channel formation semiconductor thin film portion in one cell is separated from that of its adjacent cell.    
     
     
         19 . A thin film memory array according to  claim 16 , wherein a part of the common lines is formed from a continuous second semiconductor region stretching over adjacent cells.  
     
     
         20 . A thin film memory array according to  claim 18 , 
 wherein cells are arranged such that the first semiconductor regions and the second semiconductor regions of adjacent cells form a mirror image relation to build an array, and    wherein the first and, third semiconductor regions are continued from a cell to its adjacent cell in one direction whereas the second semiconductor region is continued from a cell to its adjacent cell in the other direction.    
     
     
         21 . A thin film memory array according to  claim 16 , 
 wherein the semiconductor thin film is continuous in the word line direction, and    wherein the first semiconductor region of one cell is electrically insulated from the first semiconductor region of its adjacent cell by the third semiconductor region.    
     
     
         22 . A writing method to be applied to a thin film memory cell of  claim 12 , 
 wherein a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the second conductive gate is set to a level exceeding a gate threshold voltage Vth 2r  of a channel that is placed in the second channel formation semiconductor thin film portion to deliver opposite conductivity type carriers from the third semiconductor region which is viewed from the second conductive gate, and    wherein, by setting the electric potential difference between the second conductive gate and the third semiconductor region as above, carriers of the opposite conductivity type are implanted from the third semiconductor region through the second channel formation semiconductor thin film portion into the first channel formation semiconductor thin film portion, so that the gate threshold voltage of a first conductivity type channel in the first channel formation semiconductor thin film portion which is viewed from the first conductive gate is changed to a first value.    
     
     
         23 . A writing method to be applied to a thin film memory cell of  claim 12 , 
 wherein a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the second conductive gate is set to a level exceeding a gate threshold voltage Vth 2r  of a channel that is placed in the second channel formation semiconductor thin film portion to deliver opposite conductivity type carriers from the third semiconductor region which is viewed from the second conductive gate, and    wherein, by setting the electric potential difference between the second conductive gate and the third semiconductor region as above, carriers of the opposite conductivity type are implanted from the third semiconductor region through the second channel formation semiconductor thin film portion into the first channel formation semiconductor thin film portion, so that the gate threshold voltage of a first conductivity type channel in the first channel formation semiconductor thin film portion which is viewed from the first conductive gate is changed to a first value.    
     
     
         24 . A writing method to be applied to a thin film memory cell of  claim 12 , 
 wherein a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the second conductive gate is set to a level sufficiently exceeding a gate threshold voltage of a channel that is placed in the second channel formation semiconductor thin film portion to deliver opposite conductivity type carriers from the third semiconductor region which is viewed from the second conductive gate, and the electric potential of the third semiconductor region with respect to the same gate electric potential is set to multilevel, so that the first value of the gate threshold voltage has multilevel.    
     
     
         25 . An erasing method to be applied to a thin film memory cell of  claim 12 , 
 wherein a value obtained by subtracting, from the electric potential of the second conductive gate, the electric potential of the opposite conductivity type carriers implanted into the first channel formation semiconductor thin film portion is set to a level exceeding a gate threshold voltage of an opposite conductivity type channel in the second channel formation semiconductor thin film portion which is viewed from the second conductive gate, and    wherein, by setting the electric potential difference as above, carriers of the opposite conductivity type are drawn from the first channel formation semiconductor thin film portion into the third semiconductor region, so that the gate threshold voltage of a first conductivity type channel in the first channel formation semiconductor thin film portion which is viewed from the first conductive gate is changed to a second value.    
     
     
         26 . An erasing method to be applied to a thin film memory cell of  claim 12 , 
 wherein a value obtained by subtracting, from the electric potential of the first conductive gate, the electric potential of the opposite conductivity type carriers implanted into the first channel formation semiconductor thin film portion is set to a level exceeding a gate threshold voltage of an opposite conductivity type channel in the second channel formation semiconductor thin film portion which is viewed from the first conductive gate, and    wherein, by setting the electric potential difference as above, carriers of the opposite conductivity type are drawn from the first channel formation semiconductor thin film portion into the third semiconductor region, so that the gate threshold voltage of a first conductivity type channel in the first channel formation semiconductor thin film portion which is viewed from the first conductive gate is changed to a second value.    
     
     
         27 . An erasing method to be applied to a thin film memory cell of  claim 12 , wherein an electric potential is given in the direction that draws carriers of the opposite conductivity type to the first semiconductor region.  
     
     
         28 . An erasing method to be applied to a thin film memory cell of  claim 12 , wherein an electric potential is given in the direction that draws carriers of the opposite conductivity type to the second semiconductor region.  
     
     
         29 . An operation method to be applied to a thin film memory cell of  claim 12 , 
 wherein a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the second conductive gate is set to a level exceeding a gate threshold voltage of a channel that is placed in the second channel formation semiconductor thin film portion to deliver opposite conductivity type carriers from the third semiconductor region which is viewed from the second conductive gate,    wherein a first gate threshold voltage is written when the electric potential of the third semiconductor region is biased forward with respect to the electric potential of the second semiconductor region, and    wherein a second gate threshold voltage is written when the electric potential of the third semiconductor region is zero-biased or biased backward with respect to the same second gate voltage.    
     
     
         30 . An operation method to be applied to a thin film memory cell of  claim 12 , 
 wherein a value obtained by subtracting the electric potential of the third semiconductor region from the electric potential of the first conductive gate is set to a level exceeding a gate threshold voltage of a channel that is placed in the second channel formation semiconductor thin film portion to deliver opposite conductivity type carriers from the third semiconductor region which is viewed from the first conductive gate,    wherein a first gate threshold voltage is written when the electric potential of the third semiconductor region is biased forward with respect to the electric potential of the second semiconductor region, and    wherein a second gate threshold voltage is written when the electric potential of the third semiconductor region is zero-biased or biased backward with respect to the same first gate voltage.    
     
     
         31 . A reading method to be applied to a thin film memory cell of  claim 12 , wherein the voltage of the first conductive gate with respect to the second semiconductor region is set to a prescribed value that exceeds one or both of a first gate threshold voltage and a second gate threshold voltage and whether a current flowing between the first semiconductor region and the second semiconductor region is large or small is detected to judge stored information.  
     
     
         32 . A reading method according to  claim 31 , wherein a voltage applied between the first and second semiconductor regions does not exceed a value equal to or larger than the energy gap of the semiconductor thin film which is converted into voltage.  
     
     
         33 . An operation method to be applied to a thin film memory array of  claim 14 , 
 wherein, during writing, the word line electric potential is obtained by subtracting 0.4 V (±0.1 V) from the common line electric potential, a writing bit line electric potential is obtained by adding 0.2 V (10.1 V) to the common electric potential, and a reading bit line electric potential is the common electric potential,    wherein, during erasing, the word line electric potential is obtained by subtracting 0.5V (±0.1 V) from the common line electric potential, a writing bit line electric potential is the common electric potential, and a reading bit line electric potential is the common electric potential, and    wherein, during reading, the word line electric potential is obtained by adding 0.7 V (±0.1 V) to the common line electric potential, a writing bit line electric potential is the common electric potential, and the reading bit line electric potential is obtained by adding 0.3 V (±0.1 V) to the common electric potential.    
     
     
         34 . An operation method to be applied to a thin film memory array of  claim 16 , 
 wherein, during writing, the word line electric potential is obtained by subtracting 0.3 V (±0.1 V) from the common line electric potential, “1” writing bit line electric potential is obtained by adding 0.3 V (±0.1 V) to the common electric potential, and “0” writing bit line electric potential is obtained by subtracting 0.3 V (±0.1 V) from the common electric potential, and    wherein, during reading, the word line electric potential is obtained by adding 0.7 V (±0.1 V) to the common line electric potential and the bit line electric potential is obtained by adding 0.2 V (±0.1 V) to the common electric potential.    
     
     
         35 . A method of manufacturing a thin film memory array of  claim 16 , comprising: 
 forming a third semiconductor region through selective crystal growth;    oxidizing at least a side face of the third semiconductor region that has been formed by selective crystal growth; and    forming a first semiconductor region through selective epitaxial growth.