Embedded capacitor structure applied to logic integrated circuit

Abstract

A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

What is claimed is:  
     
         1 . An embedded capacitor device applied to a logic integrated circuit device, said embedded capacitor device comprising: 
 a substrate;    a capacitor structure is vertical on said substrate; and    a damascene structure adjacent said capacitor structure on said substrate;    
     
     
         2 . The embedded capacitor device according to  claim 1 , wherein said capacitor structure can be a vertical three-dimensional metal-insulator-metal capacitor structure.  
     
     
         3 . The embedded capacitor device according to  claim 2 , wherein said vertical three-dimensional metal-insulator-metal capacitor structure comprises: 
 a middle contact structure is electrically coupled a portion of a metal line being exposed on said substrate, wherein said portion of said metal line can be a first metal electrode plate; and    a second metal electrode plate on said middle contact structure and electrically coupled said middle contact structure.    
     
     
         4 . The embedded capacitor device according to  claim 3 , wherein said middle contact structure comprises a contact and on said metal line being exposed on said substrate.  
     
     
         5 . The embedded capacitor device according to  claim 4 , further comprising an insulator layer on sidewall of said contact.  
     
     
         6 . The embedded capacitor device according to  claim 5 , further comprising an inverse U-type contact on said insulator layer.  
     
     
         7 . The embedded capacitor device according to  claim 1 , wherein said damascene structure is electrically coupled said portion of said metal line being exposed on said substrate.  
     
     
         8 . A vertical three-dimensional metal-insulator-metal capacitor structure in a logic integrated circuit, said vertical three-dimensional metal-insulator-metal capacitor structure comprising: 
 a substrate    a first opening on a portion of a metal line being exposed on said substrate;    a first copper metal layer on said first opening to form a contact to electrically couple said portion of said metal line being exposed on said substrate;    a second opening adjacent said first opening;    an insulator layer on sidewall of said second opening;    a second copper metal layer on said insulator layer to form an inverse U-type contact; and    a second metal electrode plate on said inverse U-type contact and electrically coupled said inverse U-type contact.    
     
     
         9 . The vertical three-dimensional metal-insulator-metal capacitor structure in the logic integrated circuit according to  claim 8 , further comprising a damascene structure adjacent said vertical three-dimensional metal-insulator-metal capacitor structure on substrate.  
     
     
         10 . A method for fabricating a vertical three-dimensional capacitor structure integrated with a damascene structure, said method comprising steps of: 
 providing a substrate;    forming a first dielectric layer on said substrate;    forming a first via opening and first trench opening of said damascene structure, and a first opening within said first dielectric layer on said substrate simultaneously by using a photolithography processes;    depositing a first copper metal layer to fill with said first via opening and said first trench opening of said damascene structure to form a first layer of said damascene structure, and on said first opening to form a first contact;    forming a photoresist layer cover said damascene structure;    etching said first dielectric layer to form an inverse U-type opening;    removing said photoresist layer;    depositing a blanket insulator layer on sidewall of said inverse U-type opening;    forming a second copper metal layer to fill with said inverse U-type opening;    planarizing said second copper metal layer to form an inverse U-type contact;    depositing a second dielectric layer on the portion of said inverse U-type contact and on said damascene structure; and    forming a second layer of said damascene structure and a second metal electrode plate on said inverse U-type contact simultaneously.    
     
     
         11 . The method according to  claim 10 , wherein material of said dielectric layer can be a low dielectric constant layer.  
     
     
         12 . The method according to  claim 10 , wherein the material of said blanket insulator layer can be a high dielectric constant layer.  
     
     
         13 . The method according to  claim 12 , wherein said high dielectric constant layer is selected from the group consisting of Ta 2 O 5 , Al 2 O 3 , and BSTO.  
     
     
         14 . The method according to  claim 10 , wherein said step of forming said second copper layer comprises an electroplating method.  
     
     
         15 . The method according to  claim 10 , wherein said step of forming said second layer of said damascene structure and forming said second metal electrode plate can be the same fabricating process.