Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device

Abstract

An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.

What we claim as our invention is:  
     
         1 . An interconnect structure of a semiconductor device, comprising: 
 (a) a lower metal layer comprising a low-k dielectric material and a plurality of conductive lines, spaced apart, and extending therein, and said low-k dielectric material disposed between adjacent conductive lines;    (b) an upper metal layer comprising a low-k dielectric material, and a plurality of conductive lines, spaced apart, and extending therein, and said low-k dielectric material disposed between adjacent conductive lines;    (c) an insulating layer disposed between the lower metal layer and the upper metal layer, and comprising a low-k dielectric material;    (d) a plurality of metal-filled vias extending through the insulating layer interconnecting the conductive lines of the lower metal layer to the conductive lines of the upper metal layer; and,    (e) an ultra low-k dielectric material disposed within the low-k dielectric material of the upper metal layer and lower metal layer between adjacent conductive lines, and within the low-k dielectric material in the insulating layer.    
     
     
         2 . The interconnect structure of  claim 1  wherein said ultra low-k dielectric includes plurality of ultra low-k dielectric-filled trenches, and each said dielectric-filled trench is disposed within the low-k dielectric material between the metal lines in the upper metal layer and the lower metal layer.  
     
     
         3 . The interconnect structure of  2  wherein said ultra low-k dielectric filled trenches include trenches extending from the upper metal layer to a predetermined depth of the insulating layer, which trenches extend between the metal lines in the upper metal layer and the metal-filled vias in the insulating layer.  
     
     
         4 . The interconnect structure of  claim 1  wherein said ultra low-k dielectric material includes a plurality of ultra low-k dielectric columns spaced apart and disposed within the low-k dielectric material in the lower metal layer, upper metal layer and insulating layer.  
     
     
         5 . The interconnect structure of  claim 1  further including a first barrier layer interposed between the lower metal layer and the insulating layer and a second barrier layer disposed over the upper metal layer.  
     
     
         6 . The semiconductor device of  claim 5  wherein said first barrier layer and said second barrier layer each have a first film, and a second film disposed over the first film, wherein said first film covers the conductive lines and said ultra low-k dielectric material extends through said first film to said second film, which covers said ultra low-k dielectric material.  
     
     
         7 . A dual damascene interconnect structure of a semiconductor device, said interconnect structure, comprising: 
 (a) a lower metal layer comprising a low-k dielectric material, and a plurality of conductive lines spaced apart and extending within the low-k dielectric material;    (b) an upper metal layer comprising a low-k dielectric material and a plurality of conductive lines, spaced apart and extending within the low-k dielectric material;    (c) an insulating layer disposed between the lower metal layer and the upper metal layer, and comprising a low-k dielectric material;    (d) a plurality of metal-filled vias extending through the insulating layer interconnecting the conductive lines of the lower metal layer to the conductive lines of the upper metal layer;    (e) said upper metal layer, insulating layer and metal-filled vias are fabricated using a dual damascene process; and    (f) an ultra low-k dielectric material, disposed within the low-k dielectric material of the upper and lower metal layers between adjacent conductive lines.    
     
     
         8 . The interconnect structure of  claim 7  wherein said ultra low-k dielectric material is disposed within the low-k dielectric material in the insulating layers between adjacent metal-filled vias.  
     
     
         9 . The interconnect structure of  claim 7  further including a first barrier layer interposed between the lower metal layer and the insulating layer and a second barrier layer disposed over the upper metal layer.  
     
     
         10 . The interconnect structure of  claim 9  wherein said first barrier layer and said second barrier layer each have a first film and a second film overlaying the first film, wherein said first film covers the conductive lines and said ultra low-k dielectric material extends through said first film to said second film, which covers said ultra low-k dielectric material.  
     
     
         11 . An interconnect structure of a semiconductor device, comprising: 
 (a) at least one metal layer having a plurality of metal lines extending within a low-k dielectric material; and,    (b) a plurality of ultra low-k dielectric columns spaced apart within the low-k dielectric material between adjacent metal lines of said metal layer.    
     
     
         12 . The interconnect structure of  claim 11  further including a lower metal layer and an upper metal layer spaced above a lower metal layer, each metal layer having a plurality of metal lines extending within a low-k dielectric material, and an insulating layer disposed therebetween, and a plurality of metal-filled vias interconnecting the metal lines of the lower metal layer to the metal lines of the upper metal layer, and said ultra low-k dielectric columns extend from the upper metal layer to a predetermined depth of the insulating layer, and are spaced apart between the metal lines in the upper metal layer and the metal filled vias in the insulating layer.  
     
     
         13 . The interconnect structure of  claim 12  further including a plurality of ultra low-k dielectric columns disposed within the low-k dielectric material and between the metal lines of the lower metal layer.  
     
     
         14 . A dual damascene method of making a semiconductor device having an interconnect structure, comprising the steps of: 
 (a) forming a first metal layer having a low-k dielectric material and a plurality of conductive lines extending within the low-k dielectric material, and said conductive lines are spaced apart within said low-k dielectric material;    (b) forming a second metal layer above the first metal layer, and having a low-k dielectric material and a plurality of conductive lines extending within the low-k dielectric material, and said conductive lines are spaced apart within said dielectric material;    (c) forming an insulating layer between the first metal layer and the second metal layer, said insulating layer comprising a low-k dielectric material,    (d) interconnecting the conductive lines in the first metal layer and second metal layer with a plurality of metal-filled vias extending through the insulating layer;    (e) etching openings in the low-k dielectric material between adjacent conductive lines in the first metal layer and the second metal layer; and,    (f) depositing an ultra low-k dielectric material within the openings between the conductive lines in the first metal layer, and within the openings between the conductive metal lines of the second metal layer.    
     
     
         15 . The method of  claim 14  further including the steps of etching a plurality of openings in the insulating layer wherein each said opening is disposed between adjacent metal-filled vias, and depositing the ultra low-k dielectric material in each said opening.  
     
     
         16 . The method of  claim 14  further including the step of depositing a barrier layer between the first metal layer and the insulating layer.  
     
     
         17 . The method of  claim 14  further including the step of depositing a barrier layer over the second metal layer.  
     
     
         18 . A method of making a semiconductor device having an interconnect structure, comprising the steps of: 
 (a) forming at least one metal layer having a low-k dielectric material and a plurality of conductive lines extending within the low-k dielectric material, and said conductive lines are spaced apart within said low-k dielectric material;    (b) etching a plurality of openings in the low-k dielectric material between adjacent conductive lines in the said metal layer and said openings are spaced apart with respect to one another; and,    (c) depositing an ultra low-k dielectric material in the openings.    
     
     
         19 . The method of  claim 18  further including the step of forming a second metal layer over the first metal layer, and said first metal layer and the second metal layer having a low-k dielectric material and a plurality of conductive lines extending within the low-k dielectric material, and said conductive lines are spaced apart within said low-k dielectric material, and forming an insulating layer between the first metal layer and the second metal layer, and etching a plurality of openings between adjacent conductive lines in the second metal layer and said openings are spaced apart with respect to one another, and depositing an ultra low-k dielectric material in the openings.  
     
     
         20 . The method of  claim 18  further including the step of forming a second metal layer over the a first metal layer, and said second metal layer having a low-k dielectric material and a plurality of conductive lines extending within the low-k dielectric material, and said conductive lines are spaced apart within said low-k dielectric material, and forming an insulating layer between the first and second metal layer, interconnecting the metal lines of the first metal layer to the second metal layer with metal-filled vias, and etching a plurality of openings between adjacent conductive lines in the second metal layer and said openings extending from the second metal layer to a predetermined depth of the insulating layer, and depositing an ultra low-k dielectric material in the openings.