Method for fabricating a gate electrode

Abstract

A method for fabricating a gate electrode is disclosed. The present invention is provided a method to utilize the first nitrogen-containing RTP treatment to treat the substrate to form an interface diffusion barrier layer thereon. Then, the dielectric material has high dielectric constant that is deposited on the interface diffusion barrier layer to improve the thermal stability and chemical stability of the semiconductor substrate. Next, a barrier layer and a metal gate layer are sequentially formed on the dielectric layer. After a photolithography process, a gate electrode structure is formed on the semiconductor substrate. Thereafter, a surface inhibition layer is formed on sidewall of the gate electrode structure to improve the resistivity and thermal stability for metal gate layer after a second nitrogen-containing RTP treatment is performed on the gate electrode structure,

What is claimed is:  
     
         1 . A method for fabricating a gate electrode, wherein said method comprising: 
 providing a substrate;    forming an interface diffusion barrier layer on said substrate;    forming a dielectric layer with a high dielectric constant on said interface diffusion barrier layer;    forming a metal gate layer on said dielectric layer; and    removing portion of said metal gate layer, said dielectric layer, and said interface diffusion barrier layer to form a gate electrode on said substrate.    
     
     
         2 . The method according to  claim 1 , wherein the steps of forming said interface diffusion barrier layer comprises a first nitrogen-containing rapid thermal process.  
     
     
         3 . The method according to  claim 2 , wherein said first nitrogen-containing rapid thermal process further comprising an ammonia rapid thermal process.  
     
     
         4 . The method according to  claim 2 , wherein the temperature of said first nitrogen-containing rapid thermal process is between 600° C. to 750° C.  
     
     
         5 . The method according to  claim 2 , wherein the duration of said first nitrogen-containing rapid thermal process is between the 10 to 20 minutes.  
     
     
         6 . The method according to  claim 1 , wherein the steps of said fabricating said gate electrode on said substrate further comprising: 
 performing a post-deposition annealing to said dielectric layer;    depositing a barrier layer on said dielectric layer and a metal gate layer on said barrier layer;    forming a photoresist layer on said metal gate layer; and    sequentially etching said metal gate layer, said barrier layer, said dielectric layer, and said interface diffusion barrier layer to form a gate electrode on said substrate.    
     
     
         7 . The method according to  claim 1 , wherein material of said dielectric layer is chosen from the group consisting of zirconium dioxide (ZrO 2 ), hafnium dioxide (HfO 2 ), zirconium silicates (Zr-silicates), and hafnium silicates (Hf-silicates).  
     
     
         8 . The method according to  claim 1 , wherein said dielectric layer with said high dielectric constant is about 10.  
     
     
         9 . The method according to  claim 6 , further comprising a second nitrogen-containing rapid thermal process treatment on said gate electrode.  
     
     
         10 . The method according to  claim 9 , wherein said second nitrogen-containing rapid thermal process comprises an ammonia rapid thermal process.  
     
     
         11 . A method for fabricating a gate electrode, said method comprising: 
 providing a substrate;    treating said substrate by a first nitrogen-containing rapid thermal process to form an interface diffusion barrier layer thereon;    depositing a dielectric layer with a high dielectric constant on said interface diffusion barrier layer;    performing a post-deposition annealing process on said dielectric layer;    forming a barrier layer on said dielectric layer;    forming metal gate layer on said barrier layer;    forming a photoresist layer on said metal gate layer;    sequentially etching said metal gate layer, said barrier layer, said dielectric layer, and said interface diffusion barrier layer to form said gate electrode on said substrate; and    performing a second nitrogen-containing rapid thermal process on said gate electrode.    
     
     
         12 . The method according to  claim 11 , wherein said first nitrogen-containing rapid thermal process further comprising an ammonia rapid thermal process.  
     
     
         13 . The method according to  claim 11 , wherein said dielectric layer is chosen from the group consisting of zirconium dioxide (ZrO 2 ), hafnium dioxide (HfO 2 ), zirconium silicates (Zr-silicates), and hafnium silicates (Hf-silicates).  
     
     
         14 . The method according to  claim 11 , wherein said dielectric layer with said high dielectric constant is about 10.  
     
     
         15 . The method according to  claim 11 , wherein said performing post-deposition annealing comprises a post-deposition annealing in nitrogen gas.  
     
     
         16 . The method according to  claim 11 , wherein the material of said barrier layer comprises titanium nitride (TiN).  
     
     
         17 . The method according to  claim 11 , wherein the material of said metal gate layer comprises tantalum (Ta).  
     
     
         18 . The method according to  claim 11 , wherein said second nitrogen-containing rapid thermal process further comprising an ammonia rapid thermal process.  
     
     
         19 . A method for forming the gate electrode, said method comprising: 
 providing a substrate;    treating said substrate by a first ammonia rapid thermal process (NH 3  RTP) to form an interface diffusion barrier layer on said substrate;    chemical vapor depositing a dielectric layer on said interface diffusion barrier layer, wherein the dielectric constant of said dielectric layer is about 10;    performing a post-deposition annealing in nitrogen gas on said dielectric layer;    chemical vapor depositing a titanium nitride layer on said dielectric layer;    chemical vapor depositing a tantalum layer on said tantalum layer;    forming a photoresist layer on said tantalum layer; and    sequentially etching said tantalum layer, said titanium nitride layer, said dielectric layer, and said interface diffusion barrier layer to form a gate electrode on said substrate; and    performing a second ammonia rapid thermal process (NH 3  RTP) on said gate electrode to form a surface inhibition layer on the sidewall of said gate electrode.    
     
     
         20 . The method according to  claim 19 , wherein dielectric layer is chosen from the group consisting of zirconium dioxide (ZrO 2 ), hafnium dioxide (HfO 2 ), zirconium silicates (Zr-silicates), and hafnium silicates (Hf-silicates).  
     
     
         21 . The method according to  claim 19 , wherein the temperature of said first ammonia rapid thermal process (NH 3  RTP) is between 600° C. to 750° C.  
     
     
         22 . The method according to  claim 19 , wherein the duration of said first ammonia rapid thermal process (NH 3  RTP) is between 10 to 20 minutes.  
     
     
         23 . The method according to  claim 19 , wherein the temperature of said post-deposition annealing is between 700° C. to 900° C.  
     
     
         24 . The method according to  claim 19 , wherein the duration of said post-deposition annealing is between 20 to 45 minutes.  
     
     
         25 . The method according to  claim 19 , wherein the temperature of said second ammonia rapid thermal process is about 600° C.  
     
     
         26 . The method according to  claim 19 , wherein the duration of said second ammonia rapid thermal process is about 20 minutes.  
     
     
         27 . The method according to  claim 19 , wherein said surface inhibition layer comprises TaN x .