Semiconductor device and method of formation

Abstract

A method and apparatus for decreasing contact resistance between a ohmic contact ( 120 ) and a semiconductor material ( 106 ) are disclosed. Increased contact resistance, which occurs as a result of encroachment of the ohmic contact ( 120 ) into the semiconductor material ( 106 ) is compensated for by notching edges of the ohmic contact ( 1210 ) to increase the effective surface area between abutting surfaces of the ohmic contact ( 120 ) and semiconductor material ( 106 ). The increase in surface area increases the effective transfer length of the contact, which correspondingly reduces contact resistance and improves device performance

1 . A semiconductor device comprising a contact abutting a semiconductor material wherein the contact has a notched edge region and wherein the contact encroaches into a portion of the semiconductor material.  
     
     
         2 . The semiconductor device of  claim 1 , wherein a depth of encroachment is greater than approximately 250 Angstrom.  
     
     
         3 . The semiconductor device of  claim 2 , wherein the notched edge region increases an effective area of the contact abutting the semiconductor material, thereby reducing a contact resistance of the contact.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the semiconductor device is a field effect transistor and wherein the contact is further characterized as an ohmic contact.  
     
     
         5 . The semiconductor device of  claim 4 , wherein the ohmic contact includes a material selected from a group consisting of nickel, germanium, and gold.  
     
     
         6 . The semiconductor device of  claim 1 , wherein the semiconductor material is further characterized as a gallium arsenide capping layer.  
     
     
         7 . The semiconductor device of  claim 1  wherein the gallium arsenide capping layer is further characterized as a doped gallium arsenide capping layer.  
     
     
         8 . The semiconductor device of  claim 1 , wherein notches in the notched edge region are separated by a spacing in a range of 1 to 10 microns.  
     
     
         9 . The semiconductor of  claim 8 , wherein notches have a depth in a range of 0.5 to 5 microns and a width in a range of 0.5 to 5 microns.  
     
     
         10 . A method for forming a semiconductor device comprising: 
 forming dielectric layer over a semiconductor device substrate;    forming a patterning layer over the dielectric layer;    forming an opening in the patterning layer, wherein opening includes a patterned notched edge that extends along at least a portion of the periphery of the opening;    forming a notched contact opening in the dielectric layer;    depositing a conductive material within the notched contact opening; and    forming a notched contact structure abutting a portion of the semiconductor device.    
     
     
         11 . The method of  claim 10 , wherein forming a notched contact structure is further characterized by removing the patterning layer after depositing the conductive material.  
     
     
         12 . The method of  claim 10 , wherein forming a notched contact structure is further characterized by removing the patterning layer prior to depositing the conductive material.  
     
     
         13 . The method of  claim 10 , wherein the notched contact structure is further characterized as an ohmic contact.  
     
     
         14 . The method of  claim 13 , wherein the ohmic contact includes a material selected from a group consisting of nickel, germanium, and gold.  
     
     
         15 . The method of  claim 13 , wherein the portion of the semiconductor device is further characterized as a semiconductor-capping layer.  
     
     
         16 . The method of  claim 15 , wherein the semiconductor-capping layer is further characterized as a gallium arsenide capping layer.  
     
     
         17 . The method of  claim 16 , wherein the gallium arsenide capping layer is further characterized as a doped gallium arsenide capping layer.  
     
     
         18 . The method of  claim 15 , wherein a depth of encroachment of the ohmic contact into the semiconductor-capping layer is greater than approximately 250 Angstroms.  
     
     
         19 . The method of  claim 10 , wherein notches in the notched edge region are separated by a spacing in a range of 1 to 10 microns.  
     
     
         20 . The method of  claim 19 , wherein notches have a depth in a range of 0.5 to 5 microns and a width in a range of 0.5 to 5 microns.