Electrical communication system for a bicycle

Abstract

A circuit for a bicycle control device comprises a processor, a signal divider coupled to the processor, and a switch coupled to the signal divider so that operating the switch causes a signal input to the processor to change between at least a first signal value and a second signal value. The processor performs a first operation when the first signal value is input to the processor, and the processor performs a second operation when the second signal value is input to the processor.

What is claimed is:  
     
         1 . A circuit for a bicycle control device comprising: 
 a processor;    a signal divider coupled to the processor;    a first switch coupled to the signal divider so that operating the first switch causes a signal input to the processor to change between at least a first signal value and a second signal value; and    wherein the processor performs a first operation when the first signal value is input to the processor, and wherein the processor performs a second operation when the second signal value is input to the processor.    
     
     
         2 . The circuit according to  claim 1  wherein the second operation comprises providing a signal to cause a gear change operation.  
     
     
         3 . The circuit according to  claim 2  wherein the gear change operation comprises an upshift operation.  
     
     
         4 . The circuit according to  claim 2  wherein the gear change operation comprises a downshift operation.  
     
     
         5 . The circuit according to  claim 1  wherein the second operation comprises a mode change operation.  
     
     
         6 . The circuit according to  claim 1  wherein the signal divider comprises: 
 a first resistance; and  
 a second resistance coupled in series with the first resistance.  
 
     
     
         7 . The circuit according to  claim 6  wherein the first switch is coupled to a node between the first resistance and the second resistance.  
     
     
         8 . The circuit according to  claim 7  wherein the first signal value comprises a first voltage value, and wherein the second signal value comprises a second voltage value.  
     
     
         9 . The circuit according to  claim 1  further comprising a second switch coupled to the signal divider so that operating the second switch causes the signal input to the processor to change between the first signal value and a third signal value, wherein the processor performs a third operation when the third signal value is input to the processor.  
     
     
         10 . The circuit according to  claim 9  wherein the second operation comprises a mode change operation, and wherein the third operation comprises providing a signal to cause a gear change operation.  
     
     
         11 . The circuit according to  claim 10  wherein the gear change operation comprises an upshift operation.  
     
     
         12 . The circuit according to  claim 10  wherein the gear change operation comprises a downshift operation.  
     
     
         13 . The circuit according to  claim 10  wherein the signal divider comprises: 
 a first resistance; and  
 a second resistance coupled in series with the first resistance  
 
     
     
         14 . The circuit according to  claim 13  wherein the first switch is coupled to a node between the first resistance and the second resistance, and wherein the second switch is coupled to a node at an opposite side of the second resistance.  
     
     
         15 . The circuit according to  claim 13  wherein the signal divider comprises a third resistance coupled in series with the second resistance.  
     
     
         16 . The circuit according to  claim 15  wherein the first switch is coupled to a node between the first resistance and the second resistance, and wherein the second switch is coupled to a node between the second resistance and the third resistance.  
     
     
         17 . The circuit according to  claim 16  wherein the first signal value comprises a first voltage value, and wherein the second signal value comprises a second voltage value.  
     
     
         18 . The circuit according to  claim 9  wherein the signal divider comprises: 
 a first resistance; and  
 a second resistance coupled in series with the first resistance  
 
     
     
         19 . The circuit according to  claim 18  wherein the first switch is coupled to a node between the first resistance and the second resistance, and wherein the second switch is coupled to a node at an opposite side of the second resistance.  
     
     
         20 . The circuit according to  claim 18  wherein the signal divider comprises a third resistance coupled in series with the second resistance.  
     
     
         21 . The circuit according to  claim 20  wherein the first switch is coupled to a node between the first resistance and the second resistance, and wherein the second switch is coupled to a node between the second resistance and the third resistance.  
     
     
         22 . The circuit according to  claim 21  wherein the first signal value comprises a first voltage value, and wherein the second signal value comprises a second voltage value.