Device isolation process flow for ARS system

Abstract

A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.

What is claimed is:  
     
         1 . A method for device isolation for an atomic resolution storage (ARS) system, comprising: 
 forming an insulating layer between a wafer substrate and a top active silicon (Si) layer;    forming a phase change layer over the top active Si layer;    depositing a masking layer over the phase change layer, wherein the masking layer is patterned and selectively etched; and    etching the top active Si layer using the masking layer as a mask until reaching the insulating layer, whereby devices embedded in the top active Si layer become electrically isolated from one another.    
     
     
         2 . The method of  claim 1 , further comprising depositing a protective capping layer over the phase change layer.  
     
     
         3 . The method of  claim 1 , further comprising removing the masking layer.  
     
     
         4 . The method of  claim 1 , wherein the forming the insulating layer step comprises: 
 ion implanting oxygen beneath the top active Si layer on the wafer substrate; and    heating the oxygen to form oxide.    
     
     
         5 . The method of  claim 1 , wherein the forming the insulating layer step comprises: 
 epitaxially growing Si with counter dopants over the wafer substrate; and    heating the counter dopants.    
     
     
         6 . The method of  claim 1 , wherein the depositing step includes patterning the masking layer using photolithography.  
     
     
         7 . An apparatus with isolated devices for an atomic resolution storage (ARS) system, comprising: 
 a first wafer, wherein the first wafer includes field emitters that create electron beams by drawing electrons off a metal in the field emitters, and wherein the electron beams are used to write data bits onto storage media; and    a second wafer, wherein the second wafer is a highly doped silicon (Si) substrate, the second wafer comprises: 
 devices embedded in a top active Si layer, wherein the devices are isolated from one another, and each device is coupled with each field emitter in the second wafer; and  
 an insulating layer positioned between the second wafer substrate and the top active Si layer, wherein the devices are isolated by etching of the top active Si layer until reaching the insulating layer in the second wafer.  
   
     
     
         8 . The apparatus of  claim 7 , further comprising a phase change layer positioned above the top active Si layer.  
     
     
         9 . The apparatus of  claim 8 , further comprising a protective capping layer over the phase change layer.  
     
     
         10 . The apparatus of  claim 7 , wherein the field emitters are field emitter tips.  
     
     
         11 . The apparatus of  claim 7 , wherein the field emitters are flat emitters.  
     
     
         12 . The apparatus of  claim 7 , wherein the insulating layer is formed by heating oxygen that is ion implanted beneath the top active Si layer on the second wafer.  
     
     
         13 . The apparatus of  claim 7 , wherein the insulating layer is formed by heating counter dopants that are epitaxially grown over the second wafer.  
     
     
         14 . The apparatus of  claim 7 , wherein the second wafer is a rotor wafer.  
     
     
         15 . A method for device isolation for an atomic resolution storage (ARS) system, comprising: 
 forming an insulating layer between a wafer substrate and a top active silicon (Si) layer;    forming a phase change layer over the top active Si layer;    depositing a masking layer over the phase change layer;    patterning the masking layer;    selectively etching the masking layer; and    etching the top active Si layer using the masking layer as a mask until reaching the insulating layer, whereby devices embedded in the top active Si layer become electrically isolated from one another.    
     
     
         16 . The method of  claim 15 , further comprising depositing a protective capping layer over the phase change layer.  
     
     
         17 . The method of  claim 15 , further comprising removing the masking layer.  
     
     
         18 . The method of  claim 15 , wherein the forming the insulating layer step comprises: 
 ion implanting oxygen beneath the top active Si layer on the wafer substrate; and    heating the oxygen to form oxide.    
     
     
         19 . The method of  claim 15 , wherein the forming the insulating layer step comprises: 
 epitaxially growing Si with counter dopants over the wafer substrate; and    heating the counter dopants.    
     
     
         20 . The method of  claim 15 , wherein the patterning step includes patterning the masking layer using photolithography.