Semiconductor integrated circuit device and manufacture method therefore

Abstract

Elements in a triple-well MOS transistor are prevented from being destroyed due to an increase in current consumption or a thermal runaway of a parasitic bipolar transistor. A triple-well NMOS transistor comprising a P well area formed within an N well area and a MOSFET formed in the P well area, an impurity-diffused area having a lower impurity concentration than an N + drain area is formed close to the N+ drain area, thereby restraining substrate current. The impurity concentration of the P well area is increased to reduce the current gain of a parasitic bipolar transistor. To further reduce the current gain, a punch-through stopper area may be formed. The impurity concentration of the impurity-diffused area is set to equal that of an N − LDD area 31 of a fine CMOS device integrated on the same substrate 1 . These areas are formed during a single ion injection step.

What is claimed is:  
     
         1 . A semiconductor integrated circuit device characterized by comprising: 
 a first MOS transistor formed on a first-conductivity-type well area;    a second MOS transistor formed on a second-conductivity-type well area; and    a third MOS transistor formed on the first-conductivity-type well area that is formed within the second-conductivity-type well area, and having a second-conductivity-type drain area formed apart from a gate electrode end and a second-conductivity-type impurity-diffused area formed between said drain area and said gate electrode end, said second-conductivity-type impurity-diffused area having a lower impurity concentration than said drain area and connected to said drain area, and said first, second, and third MOS transistors being formed on the same semiconductor substrate.    
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein said third MOS transistor comprises a second-conductivity-type LDD area connected to a second-conductivity-type source area, and 
 said first MOS transistor and said second MOS transistor comprise a second-conductivity-type LDD area and a first-conductivity-type LDD area, respectively.    
     
     
         3 . The semiconductor integrated circuit device according to  claim 2 , wherein an impurity concentration of said impurity-diffused area is the same as that of said LDD areas of said third MOS transistor and said first MOS transistor.  
     
     
         4 . The semiconductor integrated circuit device according to any of  claims 1  to  3 , wherein a punch-through stopper area that restrains occurrence of a punch-through phenomenon and has a higher impurity concentration than respective said first and second conductivity type well areas is formed in each of said first-conductivity type well area having said first MOS transistor formed thereon and said second-conductivity-type well area having said second MOS transistor formed thereon.  
     
     
         5 . The semiconductor integrated circuit device according to any of  claims 1  to  3 , wherein a first-conductivity-type diffused area is formed in said first-conductivity-type well area having said third MOS transistor formed therein.  
     
     
         6 . A method of manufacturing a semiconductor integrated circuit device consisting of a first MOS transistor formed on a first-conductivity-type well area, a second MOS transistor formed on a second-conductivity-type well area, and a third MOS transistor formed on the first-conductivity-type well area that is formed in the second-conductivity-type well area, said first, second, and third MOS transistors being formed on the same semiconductor substrate, the method comprising: 
 simultaneously forming said second-conductivity-type well area of said second MOS transistor and said second-conductivity-type well area of said third MOS transistor on a main surface of said semiconductor substrate;    forming said first-conductivity-type well area of said first MOS transistor on the main surface of said semiconductor substrate;    forming said first-conductivity-type well area in said second-conductivity-type well area of said third MOS transistor and on the main surface of said semiconductor substrate;    forming a gate insulated film and a gate electrode for each of said first MOS transistor, said second MOS transistor, and said third MOS transistor;    forming an impurity-diffused area having a lower impurity concentration than a drain area, in said first-conductivity-type well area of said third MOS transistor and on the main surface of said semiconductor substrate, with a self-alignment process using said gate electrode as a mask;    simultaneously forming a source area of said first MOS transistor, a drain area of said first MOS transistor, a source area of said third MOS transistor, and said drain area of said third MOS transistor formed apart from an end of said gate electrode and connected to said impurity-diffused area; and    forming a source area and a drain area of said second MOS transistor.    
     
     
         7 . The method of manufacturing a semiconductor integrated circuit device according to  claim 6 , further comprising forming, in each of said first MOS transistor, said second MOS transistor, and said third MOS transistor, LDD areas on a source and a drain sides of said first MOS transistor, on a source and a drain sides of said second MOS transistor, and on a source side of said third MOS transistor, with a self-alignment process using said gate electrode as a mask, after said gate electrode has been formed and before said source area and said drain area are formed, the step being separate from formation of said impurity-diffused area.  
     
     
         8 . The method of manufacturing a semiconductor integrated circuit device according to  claim 6 , wherein said impurity-diffused area is formed, the LDD area is formed on each of the source and drain sides of said first MOS transistor and the source side of said third MOS transistor.  
     
     
         9 . The method of manufacturing a semiconductor integrated circuit device according to any of  claims 6  to  8 , wherein said first-conductivity-type well area of said first MOS transistor and said first-conductivity-type well area of said third MOS transistor are simultaneously formed.