Double recessed transistor

Abstract

A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of Ga x In 1-x As is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of Ga x In 1−x As is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of Al y In 1−y As is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

What is claimed is:  
     
         1 . A semiconductor structure comprising: 
 a Schottky layer adapted to be etched at a first etch rate by an etchant; and    a contact layer disposed above the Schottky layer and adapted to be etched by the etchant at a second etch rate that is substantially faster than the first etch rate;    wherein the contact layer provides an opening through the contact layer exposing a region of a top surface of the Schottky layer, the region having a first width; and    wherein the region of the top surface of the Schottky layer provides a recess of a second width smaller than the first width.    
     
     
         2 . The semiconductor recited in  claim 1  wherein the Schottky layer contains Aluminum.  
     
     
         3 . The semiconductor recited in  claim 2  wherein the Schottky layer comprises at least about 35 percent Aluminum.  
     
     
         4 . The semiconductor recited in  claim 3  wherein the Schottky layer is Al 0.6 In 0.4 As.  
     
     
         5 . The semiconductor recited in  claim 1  wherein the contact layer comprises less than about ten percent Aluminum.  
     
     
         6 . The semiconductor recited in  claim 1  wherein the contact layer is substantially free of Aluminum.  
     
     
         7 . A transistor structure comprising: 
 a Schottky layer adapted to be etched at a first etch rate by an etchant; and    a contact layer disposed above the Schottky layer and adapted to be etched by the etchant at a second etch rate that is substantially faster than the first etch rate;    wherein a region above a portion of a top surface of the Schottky layer is substantially free of the contact layer, the portion having a first width;    wherein the portion of the top surface of the Schottky layer provides a recess of a second width smaller than the first width; and    wherein the recess of the second width is adapted to receive a gate electrode.    
     
     
         8 . The transistor recited in  claim 7  wherein the Schottky layer comprises at least about 35 percent Aluminum and the contact layer comprises less than about ten percent Aluminum.  
     
     
         9 . A method of forming a semiconductor comprising: 
 forming a Schottky layer adapted to be etched by a first etchant at a first etch rate;    forming a contact layer above the Schottky layer adapted to be etched by the first etchant at a second etch rate;    applying the first etchant to etch the contact layer to expose a portion of the Schottky layer; and    applying a second etchant to etch the portion of the Schottky layer exposed by the first etchant;    wherein second etch rate is substantially faster than the first etch rate when using the first etchant.    
     
     
         10 . The method recited in  claim 9  wherein the Schottky layer contains Aluminum.  
     
     
         11 . The method recited in  claim 10  wherein the Schottky layer comprises about 35 percent Aluminum.  
     
     
         12 . The method recited in  claim 11  wherein the contact layer is substantially free of Aluminum.  
     
     
         13 . The method recited in  claim 11  wherein the first etchant includes a carboxylic-acid based wet etchant.  
     
     
         14 . The method recited in  claim 13  wherein the first etchant is succinic acid.  
     
     
         15 . The method recited in  claim 11  wherein the second etchant is applied for a predetermined time.  
     
     
         16 . A transistor structure comprising: 
 a source electrode;    a drain electrode;    a doped cap layer of Ga x In 1-x As disposed below and in ohmic contact with the source electrode and the drain electrode and providing a cap layer opening;    an undoped resistive layer of Ga x In 1-x As disposed below the cap layer and providing a resistive layer opening in registration with the cap layer opening and having a first width;    a Schottky layer of Al y In 1−y As disposed below the resistive layer;    an undoped channel layer disposed below the Schottky layer; and    a semi-insulating substrate disposed below the channel layer;    wherein a top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width; and    wherein a gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.    
     
     
         17 . The transistor recited in  claim 16  wherein the Schottky layer is doped.