Process for making low dielectric constant hollow chip structures by removing sacrificial dielectric material after the chip is joined to a carrier

Abstract

Disclosed is a multilayer integrated circuit structure joined to a chip carrier, and a process of making, in which the area normally occupied by a solid dielectric material in the IC is at least partially hollow. The hollow area can be filled with a gas, such as air, or placed under vacuum, minimizing the dielectric constant. Several embodiments and processing variants are disclosed. In one embodiment of the invention, the wiring layers, which are embedded in a temporary dielectric, alternate with via layers, also embedded in a temporary dielectric, in which the vias, besides establishing electrical communication between the wiring layers, also provide mechanical support for after the temporary dielectric is removed. Additional support is optionally provided by support structures though the interior levels and at the periphery of the chip. The temporary dielectric is removed subsequent to joining by dissolution or by ashing in an oxygen-containing plasma.

What is claimed is:  
     
         1 . An integrated circuit chip structure comprising within a plurality of via levels and a plurality of conductive wiring levels which is joined to a chip carrier and within which at least the plurality of conductive wiring levels are imbedded in a gaseous dielectric medium.  
     
     
         2 . The structure recited in  claim 1  including also a plurality of support studs strategically placed between levels within the structure and its periphery.  
     
     
         3 . An integrated circuit chip structure which is joined to a chip carrier, the chip structure comprising: a plurality of via levels and a plurality of conductive wiring levels which are imbedded in a dielectric gas and a plurality of support studs strategically placed between levels within the structure and the periphery of the structure.  
     
     
         4 . The structure recited in  claim 3 , wherein at least one via level includes a solid dielectric medium.  
     
     
         5 . The structure recited in  claim 3 , wherein the dielectric gas is selected from the group consisting of air, argon, krypton and any mixture thereof.  
     
     
         6 . In a process for fabricating a multilevel integrated circuit chip structure comprising alternating levels of conductive wiring and vias, at least one wiring level of which is imbedded in a sacrificial dielectric material, the step, subsequent to joining the structure to a chip carrier, of removing the sacrificial dielectric material.  
     
     
         7 . A process for making a multilevel IC chip structure incorporating a gas dielectric, comprising: providing a semiconductor IC chip structure which is joined to a chip carrier and which comprises alternating levels of a plurality of via levels and conductive wiring levels, at least the wiring levels of which are temporarily embedded in a solid dielectric medium which is capable of being selectively removed; and removing the solid dielectric medium.  
     
     
         8 . The process recited in  claim 7 , wherein the solid dielectric medium is selected from the group consisting of DLC, silicon oxide, polyimide, SILK, PMMA and a Novolac-type resist.  
     
     
         9 . The process recited in  claim 7  wherein the step of removing the solid dielectric medium comprises removing the solid dielectric medium by ashing or by dissolving into a solution.  
     
     
         10 . The process recited in  claim 7  wherein both the via levels and the wiring levels are temporarily imbedded in a solid dielectric medium and include support studs through the levels including the periphery.  
     
     
         11 . A process for making a multilevel IC chip structure, comprising: 
 a. providing a semiconductor device level substrate;    b. applying a first diffusion barrier/adhesive plating seed layer onto the semiconductor device level substrate;    c. applying and curing a layer of photoresist over the first seed layer;    d. exposing and developing in the photoresist a mask for a first wiring level pattern;    e. plating a conductor into the developed first wiring level pattern to form a first wiring level;    f. applying and curing a layer of photoresist onto the first wiring level;    g. exposing and developing in the photoresist a mask for a first via level pattern;    h. plating a conductor into the developed first via level pattern to form a first via level;    i. removing the undeveloped photoresist and the seed thereunder;    j. backfilling the first via level with sacrificial dielectric, curing and planarizing the dielectric to expose vias and applying a second seed layer;    k. applying and curing a layer of photoresist over the seed layer;    l. exposing and developing in the photoresist a mask for a second wiring level including any dummy support studs;    m. plating a conductor into the developed second wiring level pattern to form a second wiring level;    n. repeating steps f through m for any third and subsequent levels until the total number of levels desired has been fabricated;    o. applying a layer of permanent solid dielectric over a final wiring level, applying and curing photoresist on the permanent solid dielectric exposing and developing a pad pattern and etching through the permanent solid dielectric to open a connection between vias and pads;    p. dicing the multilevel structure into individual chips;    q. joining at least one chip to a carrier; and    r. removing all temporary resist from the at least one chip.    
     
     
         12 . The process recited in  claim 11 , wherein the step of applying a plating seed layer comprises sputtering a plating seed layer selected from a group of plating seed layers consisting of TiTa/Cu, Ti/Cu, Ta/Cu and TaN/Cu.  
     
     
         13 . The process recited in  claim 11 , wherein the step of applying and curing a layer of photoresist comprises applying and curing a layer of photoresist selected from the group consisting of methacrylate, polyimide, Novolac, azide and cyclotene-based resins.  
     
     
         14 . The process recited in  claim 11 , wherein the step of plating a conductor comprises electroplating a conductor selected from the group consisting of copper, silver, gold and alloys thereof.  
     
     
         15 . The process recited in  claim 11 , comprising, between the step of fabrication of the total number of levels desired and the step of joining, the additional step of applying a dielectric material selected from the group consisting of SiO2, DLC, Si3N4, Al nitride and organic dielectric and exposing openings for connecting preselected vias and joining pads  
     
     
         16 . The process recited in  claim 11 , wherein the step of removing photoresist comprises removing photoresist with a solvent comprising acetone or KOH or ashing in an oxygen-containing plasma.  
     
     
         17 . The process recited in  claim 11 , including the additional step, subsequent to removal of sacrificial dielectric, of applying a corrosion inhibiting coating on the conductor.  
     
     
         18 . The process recited in  claim 17 , wherein the step of applying a corrosion inhibiting coating on the conductor comprises applying a coating selected from the group consisting of Co/CO3, CoP, Ta and BTZ.  
     
     
         19 . The process recited in  claim 11 , including the additional step, prior to dicing the multilevel structure into individual chips, of annealing the multilevel structure to stabilize it.  
     
     
         20 . The process recited in  claim 11 , wherein the step of planarizing comprises chemical mechanical planarizing using alumina particles with ferric chloride, or KOH having a pH of about 9.  
     
     
         21 . The process recited in  claim 11 , wherein the step of joining comprises C4 soldering using SnPb, SnBi, SnGa or SnAu.  
     
     
         22 . The process recited in  claim 11 , wherein the step of removing the remaining temporary resist comprises blanket exposing the temporary resist and dissolving it in a photoresist developer.  
     
     
         23 . The process recited in  claim 11 , wherein the steps of plating vias and plating wiring includes the additional, subsequent step of planarizing to be even with the level of the resist.  
     
     
         24 . A process for making a multilevel chip structure, comprising: 
 a. providing a semiconductor substrate having a device level which includes planarized tungsten vias and transistors imbedded in SiO2 or SOI silicon-on-insulator;    b. applying a first diffusion barrier/adhesive plating seed layer onto the device level substrate;    c. applying and curing a first layer of photoresist over the first plating seed layer;    d. exposing and developing in the first layer of photoresist a mask for a first via level pattern; e. plating a conductor into the developed first via level pattern to form a first via level;    f. removing the remaining photoresist and the first plating seed layer thereunder;    g. depositing a semiconductor dielectric material onto the first via level and planarizing to expose the vias,    h. applying a second plating seed layer onto the planarized semiconductor dielectric material;    i. applying and curing a second layer of photoresist over the second plating seed layer;    j. exposing and developing in the second layer of photoresist a mask for a first wiring level pattern;    k. plating a conductor into the developed first wiring level pattern;    l. removing the remaining photoresist and the second plating seed layer thereunder;    m. applying a dielectric onto the first wiring level and planarizing to expose the wiring surface;    n. repeating steps b through m until the desired number of levels has been fabricated;    o. applying a final layer of DLC, preparing openings in the DLC for pad-to-via C4 plating and joining, plating conductor into the opening and plating solder onto the pads;    p. dicing the multilevel structure into chips;    q. joining at least one chip to a chip carrier; and    r. removing the dielectric from the at least one chip.    
     
     
         25 . The process recited in  claim 24 , wherein the step of applying the dielectric comprises applying a dielectric selected from the group consisting of a silicon oxide, silicon nitride, and aluminum nitride.  
     
     
         26 . The process recited in  claim 24 , wherein the step of removing the dielectric comprises preferentially dissolving the dielectric in a substantially nonaqueous composition which includes about 0.5M to about 15M of a fluoride in at least one organic solvent.