US2003205787A1PendingUtilityA1
Semiconductor device having a fuse
Priority: Mar 30, 2000Filed: Mar 30, 2001Published: Nov 6, 2003
Est. expiryMar 30, 2020(expired)· nominal 20-yr term from priority
Inventors:Norio Okada
H10W 20/494H10W 20/493H10D 89/00H10B 99/22
39
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse element is formed as a common layer with the protective cover films covering the interconnect lines.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device comprising a substrate, a first dielectric film overlying said substrate, a pair of fuse terminals embedded in a surface portion of said first dielectric film, a second dielectric film formed on said first dielectric film and said fuse terminals, said second dielectric film having a pair of openings each exposing one of said fuse terminals, a fuse element formed on said second dielectric film and connected to said pair of fuse terminals through said openings.
2 . The semiconductor device as defined in claim 1 , wherein said fuse element is made of a refractive metal.
3 . The semiconductor device as defined in claim 1 , further comprising a plurality of top interconnect lines formed as a common layer with said fuse terminals.
4 . The semiconductor device as defined in claim 1 , wherein said fuse element is made of TiN film, stacked films including a TiN film and a Ti film or a TiW film.
5 . The semiconductor device as defined in claim 1 , wherein said fuse terminals are made of Al, Al alloy, Cu or Cu alloy.
6 . A semiconductor device comprising a substrate, a first dielectric film overlying said substrate, a pair of fuse terminals embedded in a surface portion of said first dielectric film, a fuse element formed on said first dielectric film and connected to said pair of fuse terminals.
7 . The semiconductor device as defined in claim 6 , further comprising a plurality of top interconnect lines each having a line body formed as a common layer with said fuse terminals and a protective film formed on said line body as a common layer with said fuse element.
8 . The semiconductor device as defined in claim 6 , further comprising a plurality of electrode pads each having a pad body formed as a common layer with said fuse terminals and a protective film formed on said pad body as a common layer with said fuse element.
9 . The semiconductor device as defined in claim 7 , further comprising a second dielectric film formed on said first dielectric film and having a plurality of openings each exposing one of said electrode pads.
10 . The semiconductor device as defined in claim 9 , wherein said fuse element is made of TiN film, stacked films including a TiN film and a Ti film or a TiW film.
11 . The semiconductor device as defined in claim 9 , wherein said fuse terminals are made of Al, Al alloy, Cu or Cu alloy.
12 . A method for forming a semiconductor device comprising the steps of forming a first dielectric film overlying a substrate, embedding a plurality of interconnect lines and a pair of fuse terminals in a surface portion of said first dielectric film, forming a second dielectric film on said first dielectric film, said interconnect lines and said fuse terminals, selectively etching said second dielectric film to form a pair of openings each exposing one of said fuse terminals, forming a refractive metal film on said second dielectric film and said fuse terminals exposed by said opening, and patterning said refractive metal film to form a fuse element electrically connecting said fuse terminals together.
13 . A method for forming a semiconductor device comprising the steps of forming a first dielectric film overlying a substrate, embedding a plurality of interconnect lines and a pair of fuse terminals in a surface portion of said first dielectric film, forming a refractive metal film on said first dielectric film, said interconnect lines and said fuse terminals, and patterning said refractive metal film to form a fuse element electrically connecting said fuse terminals together and a plurality of protective films each formed on one of said interconnect lines.
14 . The method as defined in claim 13 , wherein said embedding step forms additionally a plurality of electrode pads, said refractive metal film forming step forms said refractive metal film on said electrode pads, and said patterning step forms a plurality of protective films each on one of said electrode pads.Join the waitlist — get patent alerts
Track US2003205787A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.