Method of fabricating a semiconductor component

Abstract

The semiconductor component is a charge carrier compensation component formed in a semiconductor body. A semiconductor basic body is disposed in the semiconductor body. The basic body has at least one compensation layer which adjoins a boundary layer and first regions of a first conductivity type and second regions of a second conductivity type are provided along a layout grid. A total quantity of charge of the first regions corresponds approximately to a total quantity of charge of the second regions. At least one semiconductor layer in the semiconductor body adjoins the semiconductor basic body at the boundary layer. A multiplicity of doped regions are embedded in the first surface of the semiconductor layer which form a grid for a cell array of the semiconductor component. The grid in the semiconductor layer is aligned independently of the layout grid in the semiconductor basic body.

We claim:  
     
         1 . A method of fabricating a semiconductor component with charge carrier compensation, which comprises the following sequential method steps: 
 a) providing a semiconductor body;    b) producing a compensation layer containing doped regions in the semiconductor body;    c) applying a semiconductor layer to the compensation layer; and    d) embedding doped regions for structures of a cell array and of an edge region of the semiconductor component in the semiconductor layer, and defining an alignment of the structures of the doped regions independently of grid alignment of the structures of the compensation layer formed by the doped regions.    
     
     
         2 . The method according to  claim 1 , which comprises producing the doped regions of the first and the second conductivity type.  
     
     
         3 . The method according to  claim 1 , which comprises etching the semiconductor body to remove a substrate of the semiconductor body.  
     
     
         4 . The method according to  claim 1 , which comprises grinding the semiconductor body to remove a substrate of the semiconductor body.  
     
     
         5 . The method according to  claim 1 , which comprises introducing the doped regions of the compensation layer at least partly by high energy implantation of ions of one of the first and of the second conductivity type into the semiconductor body.  
     
     
         6 . The method according to  claim 5 , which comprises performing the high energy implantation with different implantation energies and different implantation doses to form a substantially continuous doped region from the first surface of the semiconductor body down to a predetermined depth.  
     
     
         7 . The method according to  claim 5 , which comprises, during the high energy implantation, masking the semiconductor body with an implantation mask of a silicon wafer formed with cutouts for a passage of ions during the implantation.  
     
     
         8 . A method of fabricating a semiconductor component with charge carrier compensation, which comprises the following sequential method steps: 
 a) providing a semiconductor body with a first surface and a second surface;    b) embedding doped regions for structures of a cell array and of an edge region of the semiconductor component at the first surface;    c) producing a compensation layer containing doped regions of at least one of the first and second conductivity types in a second surface, and thereby aligning the structures of the compensation layer independently of an alignment of a grid of the structures formed by the doped regions of the cell array.    
     
     
         9 . The method according to  claim 8 , which comprises, prior to method step c), grinding the semiconductor body thin starting from the second surface.  
     
     
         10 . The method according to  claim 8 , which comprises, prior to method step c), etching the semiconductor body thin from the second surface.  
     
     
         11 . The method according to  claim 8 , which comprises applying a semiconductor layer to the semiconductor body, and embedding the doped regions in the semiconductor layer.  
     
     
         12 . The method according to  claim 8 , which comprises introducing the doped regions of the compensation layer at least partly by high energy implantation of ions of one of the first and of the second conductivity type into the semiconductor body.  
     
     
         13 . The method according to  claim 12 , which comprises performing the high energy implantation with different implantation energies and different implantation doses to form a substantially continuous doped region from the first surface of the semiconductor body down to a predetermined depth.  
     
     
         14 . The method according to  claim 12 , which comprises, during the high energy implantation, masking the semiconductor body with an implantation mask of a silicon wafer formed with cutouts for a passage of ions during the implantation.