Strained Si based layer made by UHV-CVD, and devices therein

Abstract

A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

We claim:  
     
         1 . A method for fabricating a strained Si based layer comprising the steps of: 
 growing epitaxially a SiGe layer on a substrate, wherein creating a varying Ge concentration in the thickness direction of said SiGe layer, said Ge concentration having a first value at the interface with said substrate and having a second value at full thickness of said SiGe layer, said second value of Ge concentration being larger than said first value of Ge concentration, furthermore said SiGe layer imbedding a Ge overshoot zone, wherein said Ge overshoot zone having a third value of Ge concentration, said third value being larger than said second value; and    depositing epitaxially said Si based layer onto said SiGe layer.    
     
     
         2 . The method of  claim 1 , wherein in said SiGe layer said varying Ge concentration has two regions: a step graded Ge concentration region, and a relaxed buffer region with a flat Ge concentration, said step graded region commencing at said interface with said substrate, said relaxed buffer region grown on top of said step graded region, furthermore said Ge overshoot zone being imbedded in said relaxed buffer region.  
     
     
         3 . The method of  claim 1 , wherein in said SiGe layer said varying Ge concentration is a linearly graded concentration, furthermore said Ge overshoot zone being imbedded in said linearly graded concentration, an wherein said Ge overshoot zone is nearer to said full SiGe layer thickness than to said substrate.  
     
     
         4 . The method of  claim 1 , wherein said strained Si based layer is a Si layer.  
     
     
         5 . The method of  claim 1 , wherein said strained Si based layer is a SiGe layer.  
     
     
         6 . The method of  claim 1 , wherein said strained Si based layer contains up to 5% percent of C.  
     
     
         7 . The method of  claim 1 , wherein said substrate is a Si wafer.  
     
     
         8 . The method of  claim 7 , comprising the step of creating a porous layer on the surface of said Si wafer.  
     
     
         9 . The method of  claim 7 , comprising the step of creating a porous subsurface layer on said Si wafer.  
     
     
         10 . The method of  claim 1 , wherein the thickness of said strained Si based layer is between 1 nm and 50 nm.  
     
     
         11 . The method of  claim 1 , wherein the steps of said method are carried out in an AICVD system.  
     
     
         12 . The method of  claim 1 , further comprising the step of: 
 transferring said strained Si based layer onto a second substrate.    
     
     
         13 . The method of  claim 12 , wherein said layer transfer step is an ELTRAN process.  
     
     
         14 . The method of  claim 12 , wherein said layer transfer step is a bonding, CMP polishing, and etch-back process.  
     
     
         15 . The method of  claim 12 , wherein said layer transfer step is a Smart-Cut process.  
     
     
         16 . The method of  claim 12 , wherein said second substrate is a Si wafer.  
     
     
         17 . The method of  claim 12 , wherein said second substrate has an insulating layer on its surface, and wherein said insulating surface layer receives said Si based strained layer during said layer transfer.  
     
     
         18 . The method of  claim 17 , wherein said insulating layer is silicon-oxide, silicon-nitride, aluminum-oxide, lithium-niobate, “low-k” material, “high-k” material, or combinations of two or more of said insulators.  
     
     
         19 . The method of  claim 12 , wherein the steps of said method are carried out in an AICVD system.  
     
     
         20 . A method for fabricating a strained Si based layer on an insulator comprising the steps of: 
 growing epitaxially a SiGe layer on a substrate, wherein creating a varying Ge concentration in the thickness direction of said SiGe layer, said Ge concentration having a first value at the interface with said substrate and having a second value at full thickness of said SiGe layer, said second value of Ge concentration being larger than said first value of Ge concentration, furthermore said SiGe layer imbedding a Ge overshoot zone, wherein said Ge overshoot zone having a third value of Ge concentration, said third value being larger than said second value;    depositing epitaxially said Si based layer onto said SiGe layer; and    transferring said strained Si based layer onto said insulator.    
     
     
         21 . The method of  claim 20 , wherein in said SiGe layer said varying Ge concentration has two regions: a step graded Ge concentration region, and a relaxed buffer region with a flat Ge concentration, said step graded region commencing at said interface with said substrate, said relaxed buffer region grown on top of said step graded region, furthermore said Ge overshoot zone being imbedded in said relaxed buffer region.  
     
     
         22 . The method of  claim 20 , wherein in said SiGe layer said varying Ge concentration is a linearly graded concentration, furthermore said Ge overshoot zone being imbedded in said linearly graded concentration, an wherein said Ge overshoot zone is nearer to said full SiGe layer thickness than to said substrate.  
     
     
         23 . The method of  claim 20 , wherein said strained Si based layer is a Si layer.  
     
     
         24 . The method of  claim 20 , wherein said strained Si based layer is a SiGe layer.  
     
     
         25 . The method of  claim 20 , wherein said strained Si based layer contains up to 5% percent of C.  
     
     
         26 . The method of  claim 20 , wherein said layer transfer step is an ELTRAN process.  
     
     
         27 . The method of  claim 20 , wherein said layer transfer step is a bonding, CMP polishing, and etch-back process.  
     
     
         28 . The method of  claim 20 , wherein said layer transfer step is a Smart-Cut process.  
     
     
         29 . The method of  claim 20 , wherein said insulating layer is silicon-oxide, silicon-nitride, aluminum-oxide, lithium-niobate, “low-k” material, “high-k” material, or combinations of two or more of said insulators.  
     
     
         30 . A plurality of devices manufactured in a strained Silicon based layer, wherein said strained Silicon based layer is fabricated by a method as recited in the steps of  claim 1 .  
     
     
         31 . The devices of  claim 30 , wherein said devices are FET devices.  
     
     
         32 . The devices of  claim 30 , wherein said devices are bipolar devices.  
     
     
         33 . The devices of  claim 31 , wherein said devices are interconnected into CMOS configurations.  
     
     
         34 . The devices of  claim 30 , wherein said devices are a mixture of bipolar and FET devices.  
     
     
         35 . A plurality of devices manufactured in a strained Silicon based layer, wherein said strained layer is fabricated by a method as recited in the steps of  claim 12 .  
     
     
         36 . The devices of  claim 35 , wherein said devices are FET devices.  
     
     
         37 . The devices of  claim 35 , wherein said devices are bipolar devices.  
     
     
         38 . The devices of  claim 36 , wherein said devices are interconnected into CMOS configurations.  
     
     
         39 . The devices of  claim 35 , wherein said devices are a mixture of bipolar and FET devices.  
     
     
         40 . A plurality of devices manufactured in a strained Silicon based layer, wherein said strained layer is fabricated by a method as recited in the steps of  claim 20 .  
     
     
         41 . The devices of  claim 40 , wherein said devices are FET devices.  
     
     
         42 . The devices of  claim 40 , wherein said devices are bipolar devices.  
     
     
         43 . The devices of  claim 41 , wherein said devices are interconnected into CMOS configurations.  
     
     
         44 . The devices of  claim 40 , wherein said devices are a mixture of bipolar and FET devices.  
     
     
         45 . An electronic system comprising a strained Silicon based layer, wherein said strained Silicon based layer is fabricated by a method as recited in the steps of  claim 1 .  
     
     
         46 . The electronic system of  claim 45 , wherein said electronic system is a processor.  
     
     
         47 . The processor of  claim 46 , wherein said processor is a digital processor.  
     
     
         48 . The processor of  claim 46 , wherein said processor is a wireless communication processor.  
     
     
         49 . The processor of  claim 46 , wherein said processor is an optical communication processor.  
     
     
         50 . An electronic system comprising a strained Silicon based layer, wherein said strained Silicon based layer is fabricated by a method as recited in the steps of  claim 12 .  
     
     
         51 . The electronic system of  claim 50 , wherein said electronic system is a processor.  
     
     
         52 . The processor of  claim 51 , wherein said processor is a digital processor.  
     
     
         53 . The processor of  claim 51 , wherein said processor is a wireless communication processor.  
     
     
         54 . The processor of  claim 51 , wherein said processor is an optical communication processor.  
     
     
         55 . An electronic system comprising a strained Silicon based layer, wherein said strained Silicon based layer is fabricated by a method as recited in the steps of  claim 20 .  
     
     
         56 . The electronic system of  claim 55 , wherein said electronic system is a processor.  
     
     
         57 . The processor of  claim 56 , wherein said processor is a digital processor.  
     
     
         58 . The processor of  claim 56 , wherein said processor is a wireless communication processor.  
     
     
         59 . The processor of  claim 56 , wherein said processor is an optical communication processor.