Hydrogen anneal before gate oxidation

Abstract

A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.

What is claimed is:  
     
         1 . A field-effect transistor fabrication method, comprising the steps of: 
 performing all pregate steps;    annealing a semiconductor material in a reducing atmosphere to achieve atomic-scale smoothness;    forming a dielectric on said material;    forming at least part of a thin film gate structure;    introducing a threshold-adjust dosage of dopant material through said dielectric.    
     
     
         2 . The fabrication method of  claim 1 , wherein said reducing atmosphere is an H 2  ambient of purity between 10 to 100 parts per billion.  
     
     
         3 . The fabrication method of  claim 1 , wherein said semiconductor material is a Group IV semiconductor material.  
     
     
         4 . The integrated circuit of  claim 1 , wherein said part of a thin film gate structure includes a TiN layer and a polysilicon layer.  
     
     
         5 . An integrated circuit structure formed by the method of  claim 1 .  
     
     
         6 . A field-effect transistor fabrication method, comprising the steps of: 
 performing all pregate steps;    annealing a Group IV semiconductor material in a hydrogen atmosphere to achieve atomic-scale smoothness;    forming a dielectric on said material in an oxidizing atmosphere;    forming at least part of a thin film gate structure;    implanting a threshold-adjust dosage of dopant material through said dielectric.    
     
     
         7 . The fabrication method of  claim 6 , wherein said part of a thin film gate structure includes a TiN layer and a polysilicon layer.  
     
     
         8 . The integrated circuit of  claim 6 , wherein said Group IV semiconductor is silicon.  
     
     
         9 . The integrated circuit of  claim 6 , wherein said step of forming a dielectric comprises growing a dielectric.  
     
     
         10 . An integrated circuit structure formed by the method of  claim 6 .  
     
     
         11 . A field-effect transistor fabrication method, comprising the steps of: 
 fabricating a partial transistor structure including a semiconductor channel region which separates source and drain diffusions;    annealing the surface of said channel region in a reducing atmosphere to achieve atomic-scale smoothness;    forming a gate dielectric on said channel region;    forming at least part of a thin film gate structure over said dielectric;    introducing a threshold-adjust dosage of dopant material through said dielectric.    
     
     
         12 . The fabrication method of  claim 11 , wherein said reducing atmosphere is a hydrogen reducing atmosphere.  
     
     
         13 . The fabrication method of  claim 11 , wherein said step of forming a gate dielectric is performed in an oxidizing atmosphere.  
     
     
         14 . The fabrication method of  claim 11 , wherein said part of a thin film gate structure includes a TiN layer and a polysilicon layer.  
     
     
         15 . An integrated circuit structure formed by the method of  claim 11 .  
     
     
         16 . An integrated circuit structure, comprising: 
 a substrate having a channel, the surface of said substrate having been annealed to achieve atomic-scale smoothness;    a thin film gate structure comprising a plurality of layers formed on said substrate;    wherein said channel is implanted with ions after at least one of said layers is formed.    
     
     
         17 . The integrated circuit structure of  claim 16 , wherein said substrate is annealed in a hydrogen atmosphere.  
     
     
         18 . The integrated circuit structure of  claim 16 , wherein said layers include a layer of TiN and a layer of polysilicon.