Method of manufacturing nonvolatile memory cell

Abstract

The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.

What is claimed is:  
     
         1 . A method of manufacturing a nonvolatile memory cell, comprising the steps of: 
 forming a tunnel oxide film, a floating gate electrode, a dielectric film and a control gate electrode on a semiconductor substrate;    forming source and drain region by means of source/drain ion implantation process;    forming an oxide layer on said source and drain region by means of selective oxidization process; and    forming spacers on both sides of said floating gate electrode and said the control gate electrode.    
     
     
         2 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 1 , wherein said control gate electrode is formed by stacking a polysilicon layer and tungsten nitride film (WN)/tungsten (W).  
     
     
         3 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 1 , wherein said source/drain ion implantation process is performed in a single step using an ion implantation energy of about 5 Kev˜30 keV or of about 15 KeV˜45 KeV.  
     
     
         4 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 1 , wherein said source/drain ion implantation process is performed in two steps using an ion implantation energy of about 5 KeV˜30 keV is performed and then an ion implantation energy of about 15 KeV˜45 KeV.  
     
     
         5 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 1 , wherein said oxide layer is formed in thickness of about 50 Ř400 Å.  
     
     
         6 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 1 , wherein said dielectric film is formed of a stack structure of a first oxide film, a nitride film and a second oxide film or of a single of the first oxide film.  
     
     
         7 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 1 , wherein said selective oxidization process uses hydrogen gas.  
     
     
         8 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 1 , wherein a selective oxidization process is formed on the entire structure before said source/drain ion implantation process is performed.  
     
     
         9 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 7 , wherein said selective oxidization process uses hydrogen gas.  
     
     
         10 . A method of manufacturing a nonvolatile memory cell, comprising the steps of: 
 sequentially forming a tunnel oxide film, a first polysilicon layer, a dielectric film, a second polysilicon layer, a tungsten layer and a hard mask layer a semiconductor substrate;    etching said hard mask layer, said tungsten layer, said second polysilicon layer and said dielectric film in one direction to form a control gate electrode;,    performing a first selective oxidization process to form a first oxide layer on both sides of said second polysilicon layer and said dielectric film;    forming a first spacer on both sides of said control gate electrode;    etching said first polysilicon layer and said tunnel oxide film to form a floating gate electrode;    performing source/drain ion implantation process to form a source and drain region;    performing a selective oxidization process to form a second oxide film on said source and drain region; and    forming a second spacer on both sides of said floating gate electrode and said control gate electrode.    
     
     
         11 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 10 , wherein said source/drain ion implantation process is performed in a single step using an ion implantation energy of about 5 Kev˜30 keV or of about 15 KeV˜45 KeV.  
     
     
         12 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 10 , wherein said source/drain ion implantation process is performed in two steps using an ion implantation energy of about 5 KeV˜30 keV is performed and then an ion implantation energy of about 15 KeV˜45 KeV.  
     
     
         13 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 10 , wherein said second oxide layer is formed in thickness of about 50 Ř400 Å.  
     
     
         14 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 10 , wherein said dielectric film is formed of a stack structure of a first oxide film, a nitride film and a second oxide film or of a single of the first oxide film.  
     
     
         15 . The method of manufacturing a nonvolatile memory cell as claimed in  claim 10 , wherein said first and second selective oxidization process uses hydrogen gas.