US2003202525A1PendingUtilityA1

Packet transfer apparatus, scheduler, data transfer apparatus, and packet transfer method

Assignee: FUJITSU LTDPriority: Apr 25, 2002Filed: Jan 15, 2003Published: Oct 30, 2003
Est. expiryApr 25, 2022(expired)· nominal 20-yr term from priority
H04L 49/90H04L 47/2441H04L 47/50H04L 47/2416H04L 47/6215H04L 47/2408H04L 49/9036
37
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Claims

Abstract

A packet transfer apparatus, a scheduler, a data transfer apparatus, and a packet transfer method which can control a transfer rate for each attribute according to an operational situation. When a packet is input, the buffer control circuit determines an attribute of the packet. The input packet is stored by the buffer control circuit in a buffer area which is associated with the determined attribute in advance. Thereafter, when it becomes possible to transmit a packet, the selector refers to information set in a register, and selects a buffer area which has a highest priority among at least one buffer area storing at least one packet. The selection result is sent to the buffer control circuit. Then, buffer control circuit outputs a packet stored in the selected buffer area.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A packet transfer apparatus for transferring communication packets, comprising: 
 a buffer memory partitioned into a plurality of buffer areas;    a buffer control circuit which determines at least one attribute of at least one packet which is input into said packet transfer apparatus, stores the at least one packet in at least one of said plurality of buffer areas which is respectively associated with the at least one attribute in advance, and outputs a packet stored in one of said plurality of buffer areas when said one of said plurality of buffer areas is selected;    a plurality of registers in which information indicating priorities of said plurality of buffer areas is set, where the information can be changed during packet transfer processing; and    a selector which refers to said information set in said plurality of registers at a packet transmission timing, selects one of said plurality of buffer areas which has a highest priority among at least one of said plurality of buffer areas storing at least one packet, and sends a selection result to said buffer control circuit.    
     
     
         2 . A packet transfer apparatus according to claim  1 , wherein at least one value indicating at least one boundary between the priorities is set in said at least one register.  
     
     
         3 . A packet transfer apparatus according to  claim 2 , wherein said at least one register is more than register provided for each of a plurality of boundaries between the priorities.  
     
     
         4 . A packet transfer apparatus according to  claim 1 , wherein when more than one of said plurality of buffer areas has the highest priority, said selector selects the more than one of said plurality of buffer areas in turn until no packet is left in the more than one of said plurality of buffer areas.  
     
     
         5 . A packet transfer apparatus according to  claim 4 , further comprising a table in which weights assigned to said plurality of buffer areas are set, 
 in selection of each of said plurality of buffer areas, said selector consecutively selects said each of said plurality of buffer areas a number of times corresponding to a weight assigned to said each of the plurality of buffer areas.    
     
     
         6 . A packet transfer apparatus according to  claim 1 , further comprising a packet meter which monitors a transfer rate of packets.  
     
     
         7 . A packet transfer apparatus according to  claim 6 , wherein a specification value for the transfer rate is preset in said packet meter, and the packet meter outputs an alarm when the transfer rate falls below the specification value.  
     
     
         8 . A packet transfer apparatus according to  claim 7 , wherein said specification value is preset for each attribute of packets.  
     
     
         9 . A packet transfer apparatus for transferring communication packets, comprising: 
 a plurality of buffer memories provided for each communication interface, where each of the plurality of buffer memories is partitioned into a plurality of buffer areas;    a buffer control circuit which determines at least one attribute of at least one packet which is input into said packet transfer apparatus, stores the at least one packet in at least one of said plurality of buffer areas which is respectively associated with the at least one attribute in advance, in at least one of said plurality of buffer memories corresponding to at least one communication interface to which the at least one packet is to be output, and outputs a packet stored in one of said plurality of buffer areas in one of the plurality of buffer memories when the one of the plurality of buffer areas in the one of the plurality of buffer memories is selected;    a plurality of first-stage schedulers corresponding to said plurality of buffer memories and each including a first register and a first selector, where information which indicates priorities of said plurality of buffer areas and can be varied during packet transfer processing is set in said first register, and said first selector refers to said information set in said first register at a packet transfer timing, selects one of said plurality of buffer areas which has a highest priority among at least one of the plurality of buffer areas storing at least one packet, and sends a selection result to said buffer control circuit; and    a second-stage scheduler including a second register and a second selector, where information which indicates priorities of said plurality of buffer memories and can be dynamically varied is set in said second register, and said second selector refers to said information set in said second register when a packet can be transmitted, selects one of said plurality of buffer memories which has a highest priority among at least one of the plurality of buffer memories storing at least one packet, and sends a selection result to said buffer control circuit.    
     
     
         10 . A scheduler for determining an order of transmission of packets stored in a buffer memory partitioned into a plurality of buffer areas, comprising: 
 a register in which information which indicates priorities of said plurality of buffer areas and can be varied during packet transfer processing is set; and    a selector which refers to said information set in said first register at a packet transfer timing, selects one of said plurality of buffer areas which has a highest priority among at least one of the plurality of buffer areas storing at least one packet, and determines a packet stored in the selected one of the plurality of buffer areas, to be transmitted.    
     
     
         11 . A data transfer apparatus for transferring data between a plurality of networks, comprising: 
 a first communication port;    a second communication port;    a buffer memory partitioned into a plurality of buffer areas;    a buffer control circuit which determines at least one attribute of at least one packet which is input through said first communication port, stores the at least one packet in at least one of said plurality of buffer areas which is respectively associated with the at least one attribute in advance, and outputs through said second communication port a packet stored in one of said plurality of buffer areas when the one of the plurality of buffer areas is selected;    a plurality of registers in which information indicating priorities of said plurality of buffer areas is set, where the information can be changed during packet transfer processing;    a selector which refers to said information set in said plurality of registers at a packet transmission timing, selects one of said plurality of buffer areas which has a highest priority among at least one of said plurality of buffer areas storing at least one packet, and sends a selection result to said buffer control circuit; and    a processor which dynamically changes said information set in said plurality of registers.    
     
     
         12 . A data transfer apparatus according to  claim 11 , further comprising a packet meter which monitors a transfer rate of packets.  
     
     
         13 . A data transfer apparatus according to  claim 12 , wherein a specification value for the transfer rate is preset in said packet meter, and the packet meter changes the information set in said plurality of registers.  
     
     
         14 . A packet transfer method for transferring communication packets through a buffer memory partitioned into a plurality of buffer areas, comprising the steps of: 
 (a) determining at least one attribute of at least one packet which is input, and storing the at least one packet in at least one of said plurality of buffer areas which is respectively associated with the at least one attribute in advance;    (b) at a packet transmission timing, referring to information indicating priorities of said plurality of buffer areas, and selecting one of said plurality of buffer areas which has a highest priority among at least one of said plurality of buffer areas storing at least one packet; and    (c) outputting a packet stored in the selected one of said plurality of buffer areas.

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